Abstract: A method and apparatus for controlling the flow of signals by selectively switching signals to ground and allowing signals to pass through a signal line based a position of a conductive pad. The switch contains waveguides including the signal line and at least one ground plane. The conductive pad responds to an actuation voltage to electrically connect the signal line and the ground planes when the metal pad is located in a relaxed position. When not located in the relaxed position, the switch breaks the connection to allow signals to flow through the signal line unimpeded. Brackets guide the pad as the pad moves between the relaxed position and a stimulated position due to the actuation voltage, without substantially deforming the conductive pad.

Abstract: `Unintentionally` doped P type GaAs is grown on silicon by a metal organic chemical vapor deposition process in which the molecular ratio of arsenic to gallium in the growth ambient is reduced to a value that is sufficiently low to cause the creation of donor (As) site vacancies in the grown GaAs layer, which become occupied by acceptor (carbon) atoms in the metal organic compound, thereby resulting in the formation of a buffer GaAs layer having a P type majority carrier characteristic. Preferably, the silicon substrate has its growth surface inclined from the [100] plane toward the [011] direction is initially subjected to an MOCVD process (e.g. trimethyl gallium, arsine chemical vapor deposition) at a reduced temperature (e.g. 425.degree. C.) and at atmospheric pressure, to form a thin (400 Angstroms) nucleation layer. During this growth step the Group V/Group III mole ratio (of arsenic to gallium) is maintained at an intermediate value. The temperature is then ramped to 630.degree. C.

Abstract: `Unintentionally` doped P type GaAs is grown on silicon by a metal organic chemical vapor deposition process in which the molecular ratio of arsenic to gallium in the growth ambient is reduced to a value that is sufficiently low to cause the creation of donor (As) site vacancies in the grown GaAs layer, which become occupied by acceptor (carbon) atoms in the metal organic compound, thereby resulting in the formation of a buffer GaAs layer having a P type majority carrier characteristic. Preferably, the silicon substrate has its growth surface inclined from the [100] plane toward the [011] direction is initially subjected to an MOCVD process (e.g. trimethyl gallium, arsine chemical vapor deposition) at a reduced temperature (e.g. 425.degree. C.) and at atmospheric pressure, to form a thin (400 Angstroms) nucleation layer. During this growth step the Group V/Group III mole ratio (of arsenic to gallium) is maintained at an intermediate value. The temperature is then ramped to 630.degree. C.

Abstract: There is herein described a process for fabricating GaAs FETs with an ion implanted channel layer wherein an ion implanted substrate is capless annealed under an arsine overpressure, and a relatively shallow portion of the outer surface of the substrate in the active layer is removed for the deposition of a gate metallic electrode.

Abstract: Silicon doping of GaAs epitaxial layers grown using the AsCl.sub.3 /H.sub.2 /GaAs:Ga CVD system is accomplished using AsCl.sub.3 :SiCl.sub.4 liquid doping solutions. These solutions can be readily prepared with reproducible compositions and provide excellent doping control. Fine adjustments in the doping level can be achieved by adjusting the H.sub.2 flow rate and by varying the temperature of the doping solution. Doping levels may range from about 5.times.10.sup.15 to 5.times.10.sup.19 cm.sup.-3 by adjusting the mole fraction of SiCl.sub.4 in the doping solution and the H.sub.2 flow rate to change the mole fraction of P.sub.HCl. The epitaxial layers doped using this technique have excellent room temperature and liquid nitrogen mobilities for electron concentrations between 1.times.10.sup.16 cm.sup.-3 and 8.times.10.sup.18 cm.sup.-3. This doping method is particularly useful for the growth of GaAs epitaxial layers for FET devices.

Abstract: A post-ion implantation annealing technique is provided to remove implantation damage in the active region of III-V (e.g., GaAs) semiconductor devices formed in a III-V semi-insulating substrate and separated by a field region. The technique involves applying a dielectric encapsulation selectively over the device active area and annealing in a controlled reducing atmosphere which includes the Group V element (e.g., arsenic). The dielectric encapsulant over the active region permits migration of the species employed to render the substrate semi-insulating (e.g., Cr in GaAs substrates), thereby resulting in high carrier mobility in the active region. Without encapsulation, migration of the species in the field region is substantially suppressed, thereby resulting in good inter-device isolation.