Abstract: A MOS gated device is resistant to both high radiation and SEE environments. Spaced, N-type body regions are formed in the surface of a P-type substrate of a semiconductor wafer. P-type dopants are introduced into the surface within each of the channel regions to form respective source regions therein. The periphery of each of the source regions is spaced from the periphery of its respective channel region at the surface to define N-type channel regions between the spaced peripheries. A layer of gate oxide is formed over the channel areas. A doped polysilicon gate electrode is formed atop the gate oxide. A source electrode is formed atop the source regions. The MOS gated device is optimized to maintain a threshold voltage of between ?2V to ?5V for a total irradiation dose of 300 Krad while maintaining SEE withstand capability.

Abstract: A Rad Hard MOSFET has a plurality of closely spaced base strips which have respective source to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base strips are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. An enhancement region is implanted through spaced narrow window early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) device with very low gate capacitance and very low on resistance. An early and deep (1.6 micron) P? channel implant and diffusion are formed before the main channel is formed to produce a graded body diode junction.

Abstract: A P channel vertical conduction Rad Hard MOSFET has a plurality of closely spaced base strips which have respective sources to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base stripes are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. A P type enhancement region is implanted through spaced narrow windows early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) P channel device with very low gate capacitance and very low on resistance.

Abstract: A MOSgated device is resistant to both high radiation and SEE environments. The active area of the device is formed of trench devices having a thin gate dielectric on the trench walls and a thicker dielectric on the trench bottoms over the device depletion region. Termination rings formed of ring-shaped trenches containing floating polysilicon plugs surrounds and terminates the device active area.

Abstract: A Rad Hard MOSFET has a plurality of closely spaced base strips which have respective source to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base strips are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. An enhancement region is implanted through spaced narrow window early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) device with very low gate capacitance and very low on resistance. An early and deep (1.6 micron) P channel implant and diffusion are formed before the main channel is formed to produce a graded body diode junction.

Abstract: A Schottky contact is formed in the area of a MOSgated device semiconductor device chip which is occupied by a source pad. The Schottky contact is formed by the direct contact of the aluminum source electrode to the silicon chip in the source area. A different barrier metal can be used for the Schottky. A guard ring diffusion surrounds the Schottky metal.

Abstract: Parallel, spaced SIPOS (semi-insulating polysilicon) filled trenches extend vertically through the epi layer of a MOSgated device and act to deplete carriers from the vertical conduction volume of the epi between trenches during voltage blocking conditions. Thus, a higher conductivity epi can be used to reduce the RDSON (Drain to Source ON resistance) of the device for a given break down voltage.

Abstract: A MOSgated device is resistant to both high radiation and SEE environments. The active area of the device is formed of trench devices having a thin gate dielectric on the trench walls and a thicker dielectric on the trench bottoms over the device depletion region. Termination rings formed of ring-shaped trenches containing floating polysilicon plugs surrounds and terminates the device active area.

Abstract: A MOS gated device is resistant to both high radiation and SEE environments. Spaced, N-type body regions are formed in the surface of a P-type substrate of a semiconductor wafer. P-type dopants are introduced into the surface within each of the channel regions to form respective source regions therein. The periphery of each of the source regions is spaced from the periphery of its respective channel region at the surface to define N-type channel regions between the spaced peripheries. A layer of gate oxide is formed over the channel areas. A doped polysilicon gate electrode is formed atop the gate oxide. A source electrode is formed atop the source regions. The MOS gated device is optimized to maintain a threshold voltage of between -2V to -5V for a total irradiation dose of 300 Krad while maintaining SEE withstand capability.