Abstract: Configurable processing element groups (PEGs), made up of processing elements (PEs) and boolean combiner image switches (BC), arrayed in image processing subassemblies (CAGEs) having limited external PE connections, provide myriad image processing network choices without massive investment in memory and bus capacity. PEs have full variable connectability within the PEG, and connectability via limited bus connections to PEs in related PEGs. Image switching is implemented by the BC, which is feedback connected to PEs within the PEG. Each PEG is also directly connected to the next PEG, through its BC, in straighforward pipeline configuration. For simple jobs, the implementor configures simple networks of PEs within PEGs. For demanding jobs, the implementor configures PEs in one PEG together with PEs from other PEGs, in a compound bus-connected network within the CAGE.

Abstract: A system of reconfigurable pipelines of generalized neighborhood function morphic image processors provides image transformations. An input image pixel stream is provided to one or more reconfigurable processing element groups comprising reconfigurable delay RAMs, reconfigurable neighborhood function RAMs, and reconfigurable window selection switching in order to achieve general neighborhood window function morphic image transformations. The described arrangement is amenable to VLSI packing implementation without loss of the reconfigurability or flexibility of the morphic image processor.

Abstract: Vectors on a graphics display are styled according to a specifiable pattern of on/off segments at the same time that they are drawn on the display by integrating the styling of each pixel on the vector at the same time the location of that same pixel is determined according to Bresenham's algorithm.