Abstract: A mechanism for continually testing a first processor element in a suitable multiprocessor system in which at least first and second processor elements are connected to a common input bus to concurrently receive the same opcodes and operands. Both processors decode the opcodes; when an opcode indicates an operation to be performed by the second processor, the first processor responds by executing a diagnostic operation during the second processor's execution cycle, instead of remaining idle for that time. The particular diagnostic operation to be performed is selected from among a multiplicity of available diagnostic operations. The selection is dependent on the instruction to be executed by the second processor; that is, in order to not slow down the overall execution rate of the system, a diagnostic operation is chosen whose execution time is somewhat shorter than the execution time of the instruction being performed by the second processor.