Abstract: A characterization method for a device under test includes applying a bias voltage to a test circuit. The test circuit includes a first transistor coupled to the device under test, a second transistor coupled to the device under test and to the first transistor. A third transistor is coupled to a dummy device, a fourth transistor is coupled to the dummy device and to the third transistor. The transistors are of a common type. The characterization method further includes applying non-overlapping clocking signals to transistors of the test circuit to produce test signals for application to the device under test and detecting a current in one or more transistors from the device under test. The bias voltage is further varied to characterize the device under test.

Abstract: A multiplexed transistor characterization and modeling structure for testing a plurality of transistors, The characterization and modeling structure comprises a common substrate pad, a common source pad, a plurality of drain pads, and a plurality of gate pads. The characterization and modeling structure further comprises a plurality of individual transistors. Each individual transistor comprises a substrate connected to the common substrate pad, a source connected to the common source pad, a drain connected to a single drain pad, and a gate connected to a single gate pad, wherein each individual transistor is connected to a different drain pad and gate pad combination.