Patents by Inventor Min Ae YOO

Min Ae YOO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9245796
    Abstract: A method of fabricating an interconnection structure according to an embodiment of the present invention, includes patterning a dielectric layer to form a first recession region, including a first nest-shaped recession region having a first width and a first line-shaped recession region having a second width, which is less than the first width. A guide spacer layer is formed on sidewalls of the first recession region to provide a second recession region including a second nest-shaped recession region in the first nest-shaped recession region. A self-assembling block copolymer material is formed to fill the second nest-shaped recession region. The self-assembling block copolymer material is annealed to form a polymer block domain and a polymer block matrix, surrounding the polymer block domain. The polymer block domain is removed to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is etched to form a via cavity.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: January 26, 2016
    Assignee: SK Hynix Inc.
    Inventors: Keun Do Ban, Cheol Kyu Bok, Min Ae Yoo, Jong Cheon Park
  • Patent number: 9202744
    Abstract: A method of fabricating an interconnection structure according to an embodiment of the present invention, includes patterning a dielectric layer to form a first recession region, including a first nest-shaped recession region having a first width and a first line-shaped recession region having a second width, which is less than the first width. A guide spacer layer is formed on sidewalls of the first recession region to provide a second recession region including a second nest-shaped recession region in the first nest-shaped recession region. A self-assembling block copolymer material is formed to fill the second nest-shaped recession region. The self-assembling block copolymer material is annealed to form a polymer block domain and a polymer block matrix, surrounding the polymer block domain. The polymer block domain is removed to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is etched to form a via cavity.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: December 1, 2015
    Assignee: SK Hynix Inc.
    Inventors: Keun Do Ban, Cheol Kyu Bok, Min Ae Yoo, Jong Cheon Park
  • Publication number: 20120171865
    Abstract: A method for fabricating fine patterns includes forming a first photomask including first line patterns and first assist features and forming a second photomask including second line patterns extending to a portion corresponding to the first assist features in a direction perpendicular to the first line patterns. A first resist layer may be exposed through a first exposure process by using the first photomask, and a first resist pattern formed to open regions following the shape of the first line patterns. The first resist pattern may be frozen and a second resist layer may be formed to fill the opened regions of the first resist pattern. The second resist layer may be exposed through a second exposure process by using the second photomask, and a second resist pattern formed to open regions corresponding to the intersections between the first and second line patterns with the first resist pattern.
    Type: Application
    Filed: September 23, 2011
    Publication date: July 5, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Min Ae YOO