Abstract: Disclosed is an image sensor that includes a pixel array including a plurality of unit pixels in a matrix having rows and columns, a binning sampling unit configured to (i) amplify with different gains signals from unit pixels selected from the unit pixels in each of the columns, and (ii) output a binning sampling signal according to an average of the amplified signals, and an analog-to-digital converter configured to convert the binning sampling signal to a digital signal.

Abstract: Disclosed is an image sensor that includes a pixel array including a plurality of unit pixels in a matrix having rows and columns, a binning sampling unit configured to (i) amplify with different gains signals from unit pixels selected from the unit pixels in each of the columns, and (ii) output a binning sampling signal according to an average of the amplified signals, and an analog-to-digital converter configured to convert the binning sampling signal to a digital signal.

Abstract: The present invention relates to a binary content addressable memory (CAM), and more particularly, to a binary content addressable memory (CAM) in which the number of transistors constituting the content addressable memory can be reduced to decrease the size of the content addressable memory, thereby increasing the degree of integration and improving power consumption. According to the present invention, since the binary content addressable memory according to the present invention has a smaller number of transistors than those of the conventional binary content addressable memory, a memory can be fabricated in a smaller size, thereby improving the degree of integration as one of most important factors in the memory design. In addition, improvement of the degree of integration contributes to miniaturization and lightweightness of the product in its design.

Abstract: The present invention relates to a binary content addressable memory (CAM), and more particularly, to a binary content addressable memory (CAM) in which the number of transistors constituting the content addressable memory can be reduced to decrease the size of the content addressable memory, thereby increasing the degree of integration and improving power consumption. According to the present invention, since the binary content addressable memory according to the present invention has a smaller number of transistors than those of the conventional binary content addressable memory, a memory can be fabricated in a smaller size, thereby improving the degree of integration as one of most important factors in the memory design. In addition, improvement of the degree of integration contributes to miniaturization and lightweightness of the product in its design.