Abstract: A system stores parameters of a feature extraction network and a refinement network. The system receives an input including a degraded image concatenated with a degradation estimation of the degraded image; performs operations of the feature extraction network to apply pre-trained weights to the input to generate feature maps; and performs operations of the refinement network including a sequence of dynamic blocks. One or more of the dynamic blocks dynamically generates per-grid kernels to be applied to corresponding grids of an intermediate image output from a prior dynamic block in the sequence. Each per-grid kernel is generated based on the intermediate image and the feature maps.

Abstract: A cooling system includes a rotor structure, a first end plate and a second end plate. The rotor structure includes a silicon steel, magnets and a shaft. The first end plate is at a first end of the silicon steel, and the first end plate is recessed with a first-shaped oil groove and a second-shaped oil groove. The second end plate is at a second end of the silicon steel, and the second end plate is recessed with a first-shaped oil groove and a second-shaped oil groove. The first-shaped oil groove of the first end plate is connected to the second-shaped oil groove of the second end plate to form a first cooling path. The second-shaped oil groove of the first end plate is connected to the first-shaped oil groove of the second end plate to form a second cooling path.

Abstract: Electronic design automation (EDA) of the present disclosure logically places components of the electronic circuitry onto an electronic design real estate to determine an architectural design placement for the electronic circuitry. The EDA evaluates a metaheuristic algorithm starting with an initial placement of components of the electronic circuitry onto the electronic design real estate to provide multiple possible placements for placing these components of the electronic circuitry onto the electronic design real estate. The EDA utilizes the multiple possible placements of the metaheuristic algorithm to train one or more probabilistic functions of a model-based reinforcement learning (RL) algorithm. The EDA evaluates the model-based RL algorithm utilizing the one or more probabilistic functions to determine the architectural design placement.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: According to a network space search method, an expanded search space is partitioned into multiple network spaces. Each network space includes a plurality of network architectures and is characterized by a first range of network depths and a second range of network widths. The performance of the network spaces is evaluated by sampling respective network architectures with respect to a multi-objective loss function. The evaluated performance is indicated as a probability associated with each network space. The method then identifies a subset of the network spaces that has the highest probabilities, and selects a target network space from the subset based on model complexity.

Abstract: A compensator compensates for the distortions of a power amplifier circuit. A power amplifier neural network (PAN) is trained to model the power amplifier circuit using pre-determined input and output signal pairs that characterize the power amplifier circuit. Then a compensator is trained to pre-distort a signal received by the PAN. The compensator uses a neural network trained to optimize a loss between a compensator input and a PAN output, and the loss is calculated according to a multi-objective loss function that includes one or more time-domain loss function and one or more frequency-domain loss functions. The trained compensator performs signal compensation to thereby output a pre-distorted signal to the power amplifier circuit.

Abstract: FinFET varactors having low threshold voltages and methods of making the same are disclosed herein. An exemplary FinFET varactor includes a fin and a gate structure disposed over a portion of the fin, such that the gate structure is disposed between a first source/drain feature and a second source/drain feature that include a first type dopant. The portion of the fin includes the first type dopant and a second type dopant. A dopant concentration of the first type dopant and a dopant concentration of the second type dopant vary from an interface between the fin and the gate structure to a first depth in the fin. The dopant concentration of the first type dopant is greater than the dopant concentration of the second type dopant from a second depth to a third depth in the fin, where the second depth and the third depth are less than the first depth.

Abstract: A collection and test device for a rapid test is provided. The device comprises a test fluid accommodation part having a test fluid accommodation space, a test paper accommodation part having a test paper accommodation space, and a collection probe having a channel for the test fluid to flow out from the collection probe. The two ends of the test paper accommodation part are respectively connected to the test fluid accommodation part and the collection probe, and the test paper accommodation space communicates with the channel of the collection probe. The test fluid accommodation space and the test paper accommodation space are separated from each other by a temporary barrier. The temporary barrier can be manually removed or broken to make the test fluid accommodation space communicate with the test paper accommodation space. The device of the present invention can provide the test results conveniently and rapidly.

Abstract: Disclosed is a contact lens comprising an optical region including a first area, a second area and a third area, concentrically arranged in such order from a lens center. The first area includes a correction zone having a nearsightedness correcting power. The second and third areas each include at least two defocusing zones and at least one correction zone, wherein the at least two defocusing zones and the at least one correction zone are alternatively arranged. The second area has a first power difference of ?2.00 to ?5.00 D, the third area has a second power difference of ?3.00 to ?10.00 D, and the second power difference is equal to or more negative than the first power difference.

Abstract: A voice capturing method includes following operations: storing, by a buffer, voice data from a plurality of microphones; determining, by a processor, whether a target speaker exists and whether a direction of the target speaker changes according to the voice data and target speaker information; inserting a voice segment corresponding to a previous tracking direction into a current position in the voice data to generate fusion voice data when the target speaker exists and the direction of the target speaker changes from the previous tracking direction to a current tracking direction; performing, by the processor, a voice enhancement process on the fusion voice data according to the current tracking direction to generate enhanced voice data; performing, by the processor, a voice shortening process on the enhanced voice data to generate voice output data; and playing, by a playing circuit, the voice output data.

Abstract: This invention discloses a power divider, a radio frequency transceiver and a multi-stage power divider, the power divider comprises a variable gain amplifier, a power dividing circuit, a power detection circuit and a comparison circuit. The variable gain amplifier comprises a first input terminal, a control terminal and a first output terminal, the first input terminal is configured to receive a first local oscillation signal, and the first output terminal outputs a variable output signal to the power dividing circuit. The power dividing circuit outputs a second local oscillation signal to a next stage power divider and outputs a third local oscillation signal to an up/down converter. The power detection circuit outputs a detection voltage. The comparison circuit receives a reference voltage and the detection voltage and compares the reference voltage with the detection voltage and outputs a bias voltage to the power terminal based on a comparison result.

Abstract: A robot using a liquid crystal display panel includes a mask, an LCD panel and a high-directional backlight module. The LCD is arranged close to the mask, and the backlight module is arranged on one side of the LCD panel and used to provide an extremely high directional backlight source to the liquid crystal display panel so that the image generated by the LCD panel can be projected onto the mask. By projecting images on the mask via the LCD panel, the disadvantage that the conventional projector needs to occupy a larger space is improved, and the design of the mask can be more flexible.

Abstract: A neural network (NN) processing unit includes an operation circuit to perform tensor operations of a given layer of a neural network in one of a first number representation and a second number representation. The NN processing unit further includes a conversion circuit coupled to at least one of an input port and an output port of the operation circuit to convert between the first number representation and the second number representation. The first number representation is one of a fixed-point number representation and a floating-point number representation, and the second number representation is the other one of the fixed-point number representation and the floating-point number representation.

Abstract: The invention provides an electrode body for a cylindrical lithium battery, which is formed by winding a laminated body including a negative electrode sheet, a first separator, a positive electrode sheet, a plurality of cathode tabs and a plurality of anode tabs, wherein the negative sheet and the positive sheet have a negative electrode coating and a positive electrode coating, respectively. In the present invention, the positive electrode coating is provided on the positive electrode sheet in a specific configuration to increase the coating area of the positive electrode coating, thereby increasing the capacitance of the electrode body.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: The present invention provides a display device, including: a first chromatic light source configured to generate first chromatic light, a dichroic reflection layer disposed on a light emergent side of the first chromatic light source and allowing the first chromatic light to pass through, and a quantum dot layer. The dichroic reflection layer has a first surface facing away from the first chromatic light source, and the first surface has a plurality of recessed portions. The quantum dot layer includes a plurality of quantum dot blocks, and the quantum dot blocks are disposed corresponding to the recessed portions.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: A single beam steering system and a multi-beam steering system are provided. The single beam steering system includes a fine-beam tuner and a phased array unit. The fine-beam tuner includes at least one power divider/combiner, a plurality of level controllers and a plurality of switchable inverters. The fine-beam tuner is used to control phase differences between a plurality of phased array signals of the phased array unit. The multi-beam steering system includes an N×N phased array unit, a plurality of M-channel power dividers/combiners and a plurality of the fine-beam tuners mentioned above, wherein the N is an integer greater than 1, and the M is an integer greater than 1. The fine-beam tuners are used to control phase differences between a plurality of phased array signals of the N×N phased array unit.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: FinFET varactors having low threshold voltages and methods of making the same are disclosed herein. An exemplary FinFET varactor includes a fin and a gate structure disposed over a portion of the fin, such that the gate structure is disposed between a first source/drain feature and a second source/drain feature that include a first type dopant. The portion of the fin includes the first type dopant and a second type dopant. A dopant concentration of the first type dopant and a dopant concentration of the second type dopant vary from an interface between the fin and the gate structure to a first depth in the fin. The dopant concentration of the first type dopant is greater than the dopant concentration of the second type dopant from a second depth to a third depth in the fin, where the second depth and the third depth are less than the first depth.