Abstract: An integrated circuit includes a semiconductor substrate, contact pads, testing pads, conductive posts, dummy posts, and a protection layer. The contact pads and the testing pads are distributed over the semiconductor substrate. The conductive posts are disposed on the contact pads. The dummy posts are disposed on the testing pads and are electrically floating. The protection layer covers the conductive posts and the dummy posts. A distance between top surfaces of the conductive posts and a top surface of the protection layer is smaller than a distance between top surfaces of the dummy posts and the top surface of the protection layer.

Abstract: A portable electronic device to be used as a keyless device of a vehicle includes a controlling circuit which includes a physiological feature detection module and a processing circuit. The physiological feature detection module is used for detecting a physiological feature of a person. The processing circuit is coupled to the physiological feature detection module and used for determining whether the person is an authorized user of the vehicle according to the detected physiological feature of the person, and for opening a car door of the vehicle or starting the vehicle when the person is identified by the processing circuit as the authorized user.

Abstract: Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

Abstract: A semiconductor circuit includes a first pad, a second pad, swapping circuit, and an internal circuit. The internal circuit receives a first external signal and a second external signal, and generates a first internal signal and a second internal signal. Based on master information and swapping information, the swapping circuit couples the internal circuit to one of first and second pads to provide a path through which the first internal signal is output and a path through which the first external signal is received, and couples the internal circuit to the other of the first and second pads to provide a path through which the second internal signal is output and a path through which the second external signal is received.

Abstract: A data flow classification device includes a forwarding circuit and a configuring circuit. The forwarding circuit looks the classification of an input flow up in a lookup table according to the information of the input flow, tags the packets of the input flow with the classification, and outputs the packets to a buffer circuit; but if the classification is not found in the lookup table, the forwarding circuit tags the packets with a predetermined classification, outputs the packets to the buffer circuit, and adds the information of the input flow to the lookup table. The configuring circuit determines a flow threshold according to a queue length of the buffer circuit and a target length, learns the traffic of multiple flows from the lookup table, determines the classifications of the multiple flows according to the comparison between the traffic and the flow threshold, and stores these classifications in the lookup table.

Abstract: Semiconductor devices and methods of manufacturing are provided. In some embodiments the method includes depositing an etch stop layer over a first hard mask material, the first hard mask material over a gate stack, depositing an interlayer dielectric over the etch stop layer, forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack, and treating sidewalls of the first opening with a first dopant to form a first treated region within the interlayer dielectric, a second treated region within the etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein after the treating the fourth treated region has a higher concentration of the first dopant than the first treated region.

Abstract: An electrically controlled polarization rotator is disclosed. The electrically controlled polarization rotator includes two substrates and a liquid crystal layer located between the two substrates. The two substrates have a homogeneous alignment and a homeotropic alignment respectively. A distance between the two substrates is a liquid crystal thickness. A switching electric field which is adjustable is provided between the two substrates. A polarized light is incident on the substrate having the homogeneous alignment. A polarization direction of the polarized light is orthogonal or parallel to an alignment direction of the substrate having the homogeneous alignment. A birefringence of the liquid crystal layer multiplied by the liquid crystal thickness and further divided by a wavelength of the polarized light is greater than 10. The polarization direction of the polarized light is rotated corresponding to an intensity of the switching electric field in the liquid crystal layer.

Abstract: A method for receiving a full training data set including a plurality of individual training data set, dividing the plurality of individual training sets into N classes, where N is an integer greater than three, dividing the N classes into M full data classes and N-M partial data classes, performing training to obtain a trained fixed size machine learning (ML) classification model and a trained in-class confidence model, outputting a first set of prediction value(s) based on the performance of training, distributing each class of the N classes of individual training data sets to a different node of a distributed machine learning system; and outputting, from the nodes of the distributed machine learning system, a second set of prediction value(s) for each class of the N classes.

Abstract: The present disclosure is related to an optical encoder which is configured to provide precise coding reference data by feature recognition technology. To apply the present disclosure, it is not necessary to provide particular dense patterns on a working surface. The precise coding reference data can be generated by detecting surface features of the working surface.

Abstract: A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.

Abstract: A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.

Abstract: A scented candle device includes an electromagnetic base having a casing that defines a base space and that has a top surface, and an electromagnetic unit disposed in the base space for generating a magnetic field. An electromagnetically heated scented candle is disposed on the top surface of the casing, and includes a container defining a receiving space, and a scented candle body received in the receiving space. A magnetically conductive heating member is disposed between the top surface of the casing and the container, and generates heat energy after interacting with the magnetic field of the electromagnetic unit for heating the scented candle body.

Abstract: The present disclosure provides a method for modifying a gas density relay and a gas density relay having an online self-check function and a check method therefor. The gas density relay having an online self-check function is used for high-voltage and medium-voltage electrical devices, and includes a gas density relay body, a gas density detection sensor, a gas path blocking pressure regulation mechanism, an online check contact signal sampling unit and an intelligent control unit. The intelligent control unit controls a blocking member of the gas path blocking pressure regulation mechanism to move, so as to block a gas path between a first interface and a second interface.

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

Abstract: The present invention relates to a gadolinium-based compound of a Chemical Formula 1, a method for producing the same, and an MRI contrast agent containing the same. [Chemical Formula 1] [structural formula] In chemical formula 1, A and Linker represent linking groups, and RB represents a Rose Bengal-derived part.

Abstract: CRISPR-based diagnostic methods and compositions are provided. One embodiment provides the use of DNA-barcoded antibodies or peptide-MHC (pMHC) tetramers (e.g., Kb-OVA257-264, Db-GP10025-33, Db-GP33-41) and CRISPR-Cas protein, and a guided DNA endonuclease, to achieve ultrasensitive detection of soluble and cell surface proteins. The disclosed embodiments can use type V: Cas12a; type VI: Cas13a, or Cas13b. Combining DNA encoding with CRISPR-Cas protein recognition is a sensitive system because barcodes can be isothermally amplified and Cas, for example Cas12a, enzymatically cleaves DNA reporters upon barcode detection, providing two rounds of amplification and enabling measurement of protein concentration by sample fluorescence or using by paper-based assays.

Abstract: An interlayer connective structure is suitable for being formed in a wiring board, in which the wiring board includes two traces and an insulation part between the traces. The insulation part has a through hole. The interlayer connective structure located in the through hole is connected to the traces. The interlayer connective structure includes a column and a pair of protuberant parts. The protuberant parts are located at two ends of the through hole respectively and connected to the column and the traces. The protuberant parts stick out from the outer surfaces of the traces respectively. Each of the protuberant parts has a convex curved surface, in which the distance between the convex curved surface and the axis of the through hole is less than the radius of the through hole.

Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

Abstract: An integrated circuit includes a semiconductor substrate, contact pads, testing pads, conductive posts, and dummy posts. The contact pads and the testing pads are distributed over the semiconductor substrate. The conductive posts are disposed on the contact pads. The dummy posts are disposed on the testing pads. A height of the conductive posts is greater than a height of the dummy posts.

Abstract: A projection type transparent display includes a polarization modulator and a reflective layer. The polarization modulator is stacked in sequence by a linear polarizer, a liquid crystal layer and a phase retarder. The reflective layer is stacked on the phase retarder. A projection light is incident on the linear polarizer to form a linearly polarized light. The liquid crystal layer changes a polarization direction of the linearly polarized light. Two kinds of linearly polarized projection lights with polarization directions orthogonal to each other are respectively formed and pass through the phase retarder to respectively form two kinds of circularly polarized projection lights with opposite rotation directions. A background light is incident on the reflective layer.