Patents by Inventor Min-Chen Lin

Min-Chen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11081475
    Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Hsien-Wen Liu, Min-Chen Lin
  • Publication number: 20210036405
    Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 4, 2021
    Applicant: MediaTek Inc.
    Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen, Min-Chen Lin, Hsing-Chih Liu
  • Patent number: 10847869
    Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: November 24, 2020
    Assignee: MediaTek Inc.
    Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen, Min-Chen Lin, Hsing-Chih Liu
  • Publication number: 20190355697
    Abstract: An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.
    Type: Application
    Filed: April 29, 2019
    Publication date: November 21, 2019
    Inventors: Min-Chen Lin, Yi-Hui Lee, Che-Ya Chou, Nan-Cheng Chen
  • Patent number: 10128192
    Abstract: A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Min-Chen Lin, Che-Ya Chou, Nan-Cheng Chen
  • Publication number: 20180025985
    Abstract: A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.
    Type: Application
    Filed: April 27, 2017
    Publication date: January 25, 2018
    Inventors: Min-Chen LIN, Che-Ya CHOU, Nan-Cheng CHEN
  • Publication number: 20170170161
    Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 15, 2017
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Hsien-Wen Liu, Min-Chen Lin
  • Patent number: 9583424
    Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Hsien-Wen Liu, Min-Chen Lin
  • Patent number: 8916972
    Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a thin oxide film layer directly over a top surface of the PPI structure, and a polymer layer over the thin oxide film layer and PPI structure.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Min-Chen Lin, Yi-Hang Lin
  • Publication number: 20140346665
    Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Hsien-Wen Liu, Min-Chen Lin
  • Publication number: 20140264853
    Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a thin oxide film layer directly over a top surface of the PPI structure, and a polymer layer over the thin oxide film layer and PPI structure.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Min-Chen Lin, Yi-Hang Lin