Abstract: A method and device for return instruction prediction in microprocessors and digital signal processors. The method and device uses a return target buffer, in which a return instruction address table serves to store addresses of return instructions, and a return target stack is used to store target pointers of return instructions, thereby correct prediction results can be provided in the fetch stage of a pipeline.

Abstract: An apparatus and a method of data processing system that uses multiply-accumulate instructions. The apparatus for processing data includes, a special register bank of N-bit data processing registers, a general register bank of N-bit data processing registers, a selector, a multiplier and an accumulator. The selector is coupled to the special register bank and the general register bank and is used for selecting one of the special and general register banks and outputting N-bit data from the selected register banks. The outputted N-bit data and the N-bit data held in the general register bank form a 2N-bit addition operand. The multiplier is used for performing multiply operation upon a first operand and a second operand and outputting an 2N-bit result. The accumulator is coupled to the multiplier, the selector and the general register bank and is used for performing accumulate operation upon the 2N-bit result and the 2N-bit addition operand and outputting a 2N-bit accumulated result.

Abstract: The present invention provides an instruction cache apparatus and method using the instruction read buffer. The apparatus comprises an instruction hit analysis unit, an instruction read buffer, a first cache instruction word memory, a second cache instruction word memory, a first multiplexer and a second multiplexer. The instruction hit analysis unit receives a programmable counter output signal, compares this with a plurality of tags, and after the analysis, outputs the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory. The second multiplexer reads the expected instruction word from one of either the first cache instruction word memory, the second cache instruction word memory or the first multiplexer according to the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory.

Abstract: A real time clock counter includes a serially connected plurality of register units, each register unit having a bit register for storing clock data, a half adder for incrementing the clock data stored in the bit register, and an activation circuit for activating the bit register. Each activation circuit includes a first input for receiving an oscillating timing signal and a second input for receiving a binary carry term from the previous bit register unit”s half adder. Each activation circuit also includes an output for outputting a first activation signal or a second activation signal according to the first value and the oscillating timing signal such that when the activation circuit outputs the first activation signal, the bit register is activated, and when the activation circuit outputs the second activation signal, the bit register is not activated, saving power.

Abstract: A real time clock counter includes a serially connected plurality of register units, each register unit having a bit register for storing clock data, a half adder for incrementing the clock data stored in the bit register, and an activation circuit for activating the bit register. Each activation circuit includes a first input for receiving an oscillating timing signal and a second input for receiving a binary carry term from the previous bit register unit's half adder. Each activation circuit also includes an output for outputting a first activation signal or a second activation signal according to the first value and the oscillating timing signal such that when the activation circuit outputs the first activation signal, the bit register is activated, and when the activation circuit outputs the second activation signal, the bit register is not activated, saving power.

Abstract: The present invention provides an instruction cache apparatus and method using the instruction read buffer. The apparatus comprises an instruction hit analysis unit, an instruction read buffer, a first cache instruction word memory, a second cache instruction word memory, a first multiplexer and a second multiplexer. The instruction hit analysis unit receives a programmable counter output signal, compares this with a plurality of tags, and after the analysis, outputs the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory. The second multiplexer reads the expected instruction word from one of either the first cache instruction word memory, the second cache instruction word memory or the first multiplexer according to the instruction hit signal of the instruction read buffer and the instruction hit signal of the first cache instruction word memory.

Abstract: A data processing apparatus for executing multiple instruction sets.