Abstract: A printed circuit board (PCB) for use in chip-on-board (COB) packages reduces failures due to warping of the COB packages. The PCB includes a board body having a upper surface and a lower surface, a chip bonding area on the upper surface for attaching a semiconductor device, and a plurality of conductors in a circuit pattern on the upper surface outside the chip bonding area, for electrical connection to the semiconductor device using a plurality of bonding wires. An encapsulation region encloses the chip bonding area, the bonding wires, a portion of the plurality of conductors, and a portion of the upper surface. The board includes external contacts on the lower surface for electrical connections to an external electrical appliance, and via holes through the board body for electrically connecting the plurality of conductors in the circuit pattern to the external contacts.

Abstract: A base card improves the mounting reliability of a COB package particularly when the package has molding by-products such as epoxy burrs or molding flashes. The base card has a COB package receiving part made up of first and second sections. The receiving part is stepped so that the sections thereof have shapes that are complementary to that of and for receiving a peripheral portion of the printed circuit board of the COB package and the package body the COB package, respectively. The second section has a bevel at the transition of the first section into the second section. This bevel helps define a space in which the by-products are accommodated when the COB package is mounted to the base card. Further, the second section of the COB package receiving part may define an opening in the bottom surface of the base card.

Abstract: A stacked chip package comprising an upper part including an upper semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; an upper lead frame having leads extending over the active surface of the upper semiconductor chip and which are electrically interconnected to the electrode bonding pads of the semiconductor chip; a lower part including a lower semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; a lower lead frame having inner leads extending over the active surface of the lower semiconductor chip which are electrically interconnected to the electrode bonding pads of the lower semiconductor chip, and outer leads for electrical interconnecting the stacked chip package to an external circuit device.

Abstract: A three dimensional stack package device that can realize vertical electrical interconnection of the stacked individual package devices without a cost increase or additional complicated processing steps.