Patents by Inventor Min Chiang Chen

Min Chiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145650
    Abstract: A package comprises a substrate including a first surface, and an upper conductive layer arranged on the first surface, a first light-emitting unit arranged on the upper conductive layer, and comprises a first semiconductor layer, a first substrate, a first light-emitting surface and a first side wall, a second light-emitting unit, which is arranged on the upper conductive layer, and comprises a second light-emitting surface and a second side wall, a light-transmitting layer arranged on the first surface and covers the upper conductive layer, the first light-emitting unit, and the second light-emitting unit, a light-absorbing layer, which is arranged between the substrate and the light-transmitting layer in a continuous configuration of separating the first light-emitting unit and the second light-emitting unit from each other, and a reflective wall arranged on the first side wall, wherein a height of the reflective wall is lower than that of the light-absorbing layer.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Inventors: Shau-Yi CHEN, Tzu-Yuan LIN, Wei-Chiang HU, Pei-Hsuan LAN, Min-Hsun HSIEH
  • Publication number: 20240128261
    Abstract: A structure and method for improving manufacturing yield of passive device dies are disclosed. The structure includes first and second groups of capacitors disposed on a substrate, an interconnect structure disposed on the first and second groups of capacitors, first and second bonding structures disposed on the first and second conductive lines, respectively, and first and second measurement structures connected to the first and second conductive lines, respectively, and configured to measure electrical properties of the first and second groups of capacitors, respectively. The interconnect structure includes first and second conductive line connected to the first and second groups of trench capacitors, respectively. The first bonding structure is electrically connected to the first group of capacitors and the second bonding structure is electrically isolated from the first and second groups of capacitors. The first and second measurement structures are electrically isolated from each other.
    Type: Application
    Filed: March 29, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Chiang KUO, Yu-Hsin Fang, Min-Hsiung Chen
  • Patent number: D568246
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: May 6, 2008
    Assignee: Cheng Uei Precision Industry Co., Ltd.
    Inventors: Yin Lung Wu, Min Chiang Chen, Min Song
  • Patent number: D568250
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: May 6, 2008
    Assignee: Cheng Uei Precision Industry Co., Ltd.
    Inventors: Yin-Lung Wu, Min-Chiang Chen, Wei-hong Liao