Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.

Abstract: A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer.

Abstract: A phase change memory device is provided, including a substrate, a first dielectric layer disposed over the substrate, a first electrode disposed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, covering the first electrode, a heating electrode disposed in the second dielectric layer, contacting the first electrode, a phase change material layer disposed over the second dielectric layer, contacting the heating electrode, and a second electrode disposed over the phase change material layer. In one embodiment, the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides and the first portion of the heating electrode includes no metal silicides.

Abstract: A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer.

Abstract: A phase change memory device is provided, including a substrate, a first dielectric layer disposed over the substrate, a first electrode disposed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, covering the first electrode, a heating electrode disposed in the second dielectric layer, contacting the first electrode, a phase change material layer disposed over the second dielectric layer, contacting the heating electrode, and a second electrode disposed over the phase change material layer. In one embodiment, the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides and the first portion of the heating electrode includes no metal silicides.

Abstract: A method for avoiding copper extrusion during a damascene process is disclosed. A semiconductor wafer including a substrate with at least one copper conductive wire on the substrate is provided. A dielectric layer on the copper conductive wire is formed. A damascene structure having an opening exposing a portion of the copper conductive wire is formed using the dielectric layer. A degassing process to make gas escape from the dielectric layer is performed. A barrier layer on portions of the exposed surface of the copper conductive wire and the damascene structure of the dielectric layer is formed. A conductive layer on the barrier layer is formed.

Abstract: A method for avoiding copper extrusion during a damascene process is disclosed. A semiconductor wafer including a substrate with at least one copper conductive wire on the substrate is provided. A dielectric layer on the copper conductive wire is formed. A damascene structure having an opening exposing a portion of the copper conductive wire is formed using the dielectric layer. A degassing process to make gas escape from the dielectric layer is performed. A barrier layer on portions of the exposed surface of the copper conductive wire and the damascene structure of the dielectric layer is formed. A conductive layer on the barrier layer is formed.

Abstract: A vehicular external mirror assembly includes a casing having a mirror unit and a tubular member. A first tube has a twisted oblique elongated slot extending longitudinally between a first open top and a first open bottom end of the first tube. The tubular member is slidably sleeved onto the first tube. A threaded rotatable shaft is mounted in the first tube. An elevating unit includes an annular member threadably engaging the rotatable shaft. The annular member has a radial stud projecting through said elongated slot slidably to engage the same and being connected to the tabular member of the casing. An electrical driving unit connected to a lower end of the rotatable shaft includes a motor and a gear assembly interconnecting the lower end of the rotatable shaft and the motor.