Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.

Abstract: A forming method of a resistive memory device is provided. The forming method includes: conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state and measuring a first current of the resistive memory device; performing a thermal step on the resistive memory device and measuring a second current of the resistive memory device; and comparing the second current to the first current and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current. In addition, a memory storage apparatus including a resistive memory device is also provided.

Abstract: A resistive memory and a resistance window recovery method for a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between a top electrode and a bottom electrode of the resistive memory cell, wherein the over reset voltage difference falls in a reset complementary switching (reset-CS) voltage range of the resistive memory cell. During a second period, a set voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell to increase a compliance current of the resistive memory cell. During a third period, a reset operation is performed on the resistive memory cell.

Abstract: A forming method of a resistive memory device is provided. The forming method includes: conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state and measuring a first current of the resistive memory device; performing a thermal step on the resistive memory device and measuring a second current of the resistive memory device; and comparing the second current to the first current and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current. In addition, a memory storage apparatus including a resistive memory device is also provided.

Abstract: A resistive memory apparatus and a setting method for a resistive memory cell thereof are provided. The setting method includes: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is finished; determining whether to perform a first resetting operation on the resistive memory cell according to a verifying result of the first verifying operation, and performing a second verifying operation on the resistive memory cell after the first resetting operation is determined to be performed and is finished; and determining whether to perform a second resetting operation on the resistive memory cell according to a verifying result of the second verifying operation, and performing a third verifying operation on the resistive memory cell after the second resetting operation is determined to be performed and is finished.

Abstract: A resistive memory apparatus and a setting method for a resistive memory cell thereof are provided. The setting method includes: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is finished; determining whether to perform a first resetting operation on the resistive memory cell according to a verifying result of the first verifying operation, and performing a second verifying operation on the resistive memory cell after the first resetting operation is determined to be performed and is finished; and determining whether to perform a second resetting operation on the resistive memory cell according to a verifying result of the second verifying operation, and performing a third verifying operation on the resistive memory cell after the second resetting operation is determined to be performed and is finished.

Abstract: A resistive memory and a resistance window recovery method for a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between a top electrode and a bottom electrode of the resistive memory cell, wherein the over reset voltage difference falls in a reset complementary switching (reset-CS) voltage range of the resistive memory cell. During a second period, a set voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell to increase a compliance current of the resistive memory cell. During a third period, a reset operation is performed on the resistive memory cell.

Abstract: A method of manufacturing a flexible substrate structure includes the following steps. A first loading substrate having a center area and a peripheral area is provided. A first adhesive layer is formed on the center area of the first loading substrate, and a second adhesive layer is formed on the peripheral area of the first loading substrate. The first flexible substrate is adhered to the first loading substrate by the first adhesive layer and the second adhesive layer to form a flexible substrate structure, wherein the adhesive force between the first flexible substrate and the second adhesive layer is stronger than that between the first flexible substrate and the first adhesive layer. The flexible substrate structure is cut, and the first flexible substrate is separated from the flexible substrate structure.

Abstract: A substrate manufacturing method includes steps of: providing a transparent substrate; applying an adhesive layer to a surface of the transparent substrate; disposing a flexible substrate on the adhesive layer to form a multi-layer structure; disposing the multi-layer structure over the reflector, in which the reflector has a first reflecting region and a second reflecting region, and the reflectivity of the first reflecting region is greater than the reflectivity of the second reflecting region; and hardening the adhesive layer by performing an ultraviolet radiation toward the multi-layer structure to form a first hardened portion and a second hardened portion.

Abstract: A method of manufacturing a flexible substrate structure includes the following steps. A first loading substrate having a center area and a peripheral area is provided. A first adhesive layer is formed on the center area of the first loading substrate, and a second adhesive layer is formed on the peripheral area of the first loading substrate. The first flexible substrate is adhered to the first loading substrate by the first adhesive layer and the second adhesive layer to form a flexible substrate structure, wherein the adhesive force between the first flexible substrate and the second adhesive layer is stronger than that between the first flexible substrate and the first adhesive layer. The flexible substrate structure is cut, and the first flexible substrate is separated from the flexible substrate structure.