Patents by Inventor Min Chin Chai

Min Chin Chai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9705495
    Abstract: An embodiment of a capacitive sensor array may comprise a first plurality of sensor elements and a second sensor element comprising a main trace that intersects each of the first plurality of sensor elements to form a plurality of intersections. A unit cell may be associated with each of the intersections, and each unit cell may designate a set of locations nearest to a corresponding intersection. A contiguous section of the main trace may cross at least one of the plurality of unit cells. The capacitive sensor array may further comprise a plurality of open zones, where each of the plurality of open zones is staggered relative to an adjacent open zone.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: July 11, 2017
    Assignee: Creator Technology B.V.
    Inventors: Min Chin Chai, Patrick Prendergast, Massoud Badaye
  • Patent number: 9513755
    Abstract: A sensor array includes a first sensor element of a unit cell and a second sensor element of the unit cell. The unit cell includes core traces of the first sensor element, where the core traces are the widest portion of the first sensor element. The unit cell includes main traces of the second sensor element and subtraces of the second sensor element, where each main trace crosses the first sensor element at a corresponding bridge to form an intersection of the unit cell.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: December 6, 2016
    Assignee: Creator Technology B.V.
    Inventors: Min Chin Chai, Patrick Prendergast, Tao Peng
  • Patent number: 9201106
    Abstract: A self-shielding capacitive sensor array may include a first plurality of sensor elements and a second plurality of sensor elements, where each of the second plurality of sensor elements intersects each of the first plurality of sensor elements, such that each of the first plurality of sensor elements may be capacitively coupled with each of the second plurality of sensor elements. The first plurality of sensor elements may be configured to shield each of the second plurality of sensor elements from a noise source.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: December 1, 2015
    Assignee: PARADE TECHNOLOGIES, LTD.
    Inventors: Min Chin Chai, Fred Keiser, Igor Polishchuk
  • Patent number: 9116581
    Abstract: A capacitive sense array configured to improve edge accuracy in detecting a presence of a conductive object is described. In one embodiment, a capacitive sense array includes at least a first set of sense elements having non-homogenous pitches disposes in a first longitudinal axis of the capacitive sense array. The pitch includes width of the sense elements and spacing between the sense elements.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: August 25, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Tao Peng, Min Chin Chai
  • Publication number: 20150193050
    Abstract: A sensor array includes a first sensor element of a unit cell and a second sensor element of the unit cell. The unit cell includes core traces of the first sensor element, where the core traces are the widest portion of the first sensor element. The unit cell includes main traces of the second sensor element and subtraces of the second sensor element, where each main trace crosses the first sensor element at a corresponding bridge to form an intersection of the unit cell.
    Type: Application
    Filed: December 1, 2014
    Publication date: July 9, 2015
    Inventors: Min Chin Chai, Patrick Prendergast, Tao Peng
  • Patent number: 8952892
    Abstract: One or more input location correction tables are used to compensate for interference introduced into input panels and generate a corrected location based on a sensed location of the input panel. The one or more input location correction tables can include a coarse table and a fine table that stores mappings of intermediate locations mapped to by the coarse table having an accuracy that fails to satisfy a threshold coordinate accuracy. Different environments in which computing device can be situated can result in different interference being introduced, and the one or more input location correction tables can be updated based on the current environment to compensate for the interference introduced in the current environment.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: February 10, 2015
    Assignee: Microsoft Corporation
    Inventor: Min Chin Chai
  • Patent number: 8901944
    Abstract: One embodiment of a capacitive sensor array may comprise a first plurality of sensor elements and a second sensor element comprising a main trace, where the main trace intersects each of the first plurality of sensor elements to form a plurality of intersections. A unit cell may be associated with each of the intersections, and each unit cell may designate a set of locations nearest to the corresponding intersection. A contiguous section of the main trace may cross at least one of the plurality of unit cells. Within each unit cell, the second sensor element may comprise at least one primary subtrace branching away from the main trace.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: December 2, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Min Chin Chai, Patrick Prendergast, Tao Peng
  • Publication number: 20140118241
    Abstract: One or more input location correction tables are used to compensate for interference introduced into input panels and generate a corrected location based on a sensed location of the input panel. The one or more input location correction tables can include a coarse table and a fine table that stores mappings of intermediate locations mapped to by the coarse table having an accuracy that fails to satisfy a threshold coordinate accuracy. Different environments in which computing device can be situated can result in different interference being introduced, and the one or more input location correction tables can be updated based on the current environment to compensate for the interference introduced in the current environment.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 1, 2014
    Applicant: MICROSOFT CORPORATION
    Inventor: Min Chin Chai
  • Patent number: 8482546
    Abstract: A self-shielding capacitive sensor array may include a first plurality of sensor elements and a second plurality of sensor elements, where each of the second plurality of sensor elements intersects each of the first plurality of sensor elements, such that each of the first plurality of sensor elements may be capacitively coupled with each of the second plurality of sensor elements. The first plurality of sensor elements may be configured to shield each of the second plurality of sensor elements from a noise source.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: July 9, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Min Chin Chai, Fred Keiser, Igor Polishchuk
  • Publication number: 20130049771
    Abstract: A capacitive sense array configured to improve edge accuracy in detecting a presence of a conductive object is described. In one embodiment, a capacitive sense array includes at least a first set of sense elements having non-homogenous pitches disposes in a first longitudinal axis of the capacitive sense array. The pitch includes width of the sense elements and spacing between the sense elements.
    Type: Application
    Filed: September 1, 2011
    Publication date: February 28, 2013
    Inventors: Tao Peng, Min Chin Chai
  • Publication number: 20120133611
    Abstract: An embodiment of a capacitive sensor array may comprise a first plurality of sensor elements and a second sensor element comprising a main trace that intersects each of the first plurality of sensor elements to form a plurality of intersections. A unit cell may be associated with each of the intersections, and each unit cell may designate a set of locations nearest to a corresponding intersection. A contiguous section of the main trace may cross at least one of the plurality of unit cells. The capacitive sensor array may further comprise a plurality of open zones, where each of the plurality of open zones is staggered relative to an adjacent open zone.
    Type: Application
    Filed: September 28, 2011
    Publication date: May 31, 2012
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Min Chin Chai, Massoud Badaye, Patrick Prendergast
  • Publication number: 20120044198
    Abstract: A self-shielding capacitive sensor array may include a first plurality of sensor elements and a second plurality of sensor elements, where each of the second plurality of sensor elements intersects each of the first plurality of sensor elements, such that each of the first plurality of sensor elements may be capacitively coupled with each of the second plurality of sensor elements. The first plurality of sensor elements may be configured to shield each of the second plurality of sensor elements from a noise source.
    Type: Application
    Filed: June 29, 2011
    Publication date: February 23, 2012
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Min Chin Chai, Fred Keiser, Igor Polishchuk
  • Publication number: 20110316567
    Abstract: One embodiment of a capacitive sensor array may comprise a first plurality of sensor elements and a second sensor element comprising a main trace, where the main trace intersects each of the first plurality of sensor elements to form a plurality of intersections. A unit cell may be associated with each of the intersections, and each unit cell may designate a set of locations nearest to the corresponding intersection. A contiguous section of the main trace may cross at least one of the plurality of unit cells. Within each unit cell, the second sensor element may comprise at least one primary subtrace branching away from the main trace.
    Type: Application
    Filed: August 5, 2011
    Publication date: December 29, 2011
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Min Chin Chai, Patrick Prendergast