Patents by Inventor Min-Chin Yang

Min-Chin Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7324508
    Abstract: A crossbar switching circuit and operating method thereof for coupling a plurality of source providers to a plurality of source consumers based on the request of the source consumer are provided. The crossbar switching circuit includes a plurality of source consumer terminals coupled to the source consumers respectively, a plurality of source provider terminals coupled to the source providers respectively, a plurality of first counters and a plurality of second counters. Wherein, each source consumer terminal has one first counter and one second counter. The first counter indicates a current latency state of the resource requested by the corresponding source consumer. The second counter indicates a current bandwidth state of resource requested by the corresponding source consumer. In addition, the connecting states between the source consumer terminals and the source provider terminals are determined based on the states of the first counters and the second counters.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: January 29, 2008
    Assignee: Faraday Technology Corp.
    Inventors: Ching-Jer Liang, Min-Chin Yang
  • Publication number: 20060198366
    Abstract: A crossbar switching circuit and operating method thereof for coupling a plurality of source providers to a plurality of source consumers based on the request of the source consumer are provided. The crossbar switching circuit includes a plurality of source consumer terminals coupled to the source consumers respectively, a plurality of source provider terminals coupled to the source providers respectively, a plurality of first counters and a plurality of second counters. Wherein, each source consumer terminal has one first counter and one second counter. The first counter indicates a current latency state of the resource requested by the corresponding source consumer. The second counter indicates a current bandwidth state of resource requested by the corresponding source consumer. In addition, the connecting states between the source consumer terminals and the source provider terminals are determined based on the states of the first counters and the second counters.
    Type: Application
    Filed: March 1, 2005
    Publication date: September 7, 2006
    Inventors: Ching-Jer Liang, Min-Chin Yang
  • Patent number: 6963231
    Abstract: An insulating device for system on chip (SOC). The SOC has a first circuit region powered by a main power source and a second circuit region powered by a real-time power source. In the insulating device, a selector designates the main power source or a battery source as a real-time power source. A level detector detects a voltage level of the main power source and outputs a resulting signal. A NAND gate produces a logic output according to the result signal and an output signal of the first circuit. The NAND gate includes first and second PMOS transistors and first and second NMOS transistors. Gates of the first PMOS transistor and the first NMOS transistor are directly connected to the output signal of the first circuit without through any buffers. Gates of the second PMOS transistor and the second NMOS transistor are directly connected to the result signal without any buffers.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: November 8, 2005
    Assignee: Faraday Technology Corp.
    Inventor: Min-Chin Yang
  • Publication number: 20050179474
    Abstract: An insulating device for system on chip (SOC). The SOC has a first circuit region powered by a main power source and a second circuit region powered by a real-time power source. In the insulating device, a selector designates the main power source or a battery source as a real-time power source. A level detector detects a voltage level of the main power source and outputs a resulting signal. A NAND gate produces a logic output according to the result signal and an output signal of the first circuit. The NAND gate includes first and second PMOS transistors and first and second NMOS transistors. Gates of the first PMOS transistor and the first NMOS transistor are directly connected to the output signal of the first circuit without through any buffers. Gates of the second PMOS transistor and the second NMOS transistor are directly connected to the result signal without any buffers.
    Type: Application
    Filed: February 17, 2004
    Publication date: August 18, 2005
    Inventor: Min-Chin Yang