Abstract: A thin-film photovoltaic device comprising at least: a substrate, a transparent electrode layer, a p-type semiconductor as the ohmic contact layer, an intrinsic semiconductor as the light absorption layer, and a magnesium alloy substituted for the n-type semiconductor as the other ohmic contact layer. A method for manufacturing the thin-film photovoltaic device is also provided in the present invention.

Abstract: A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level.

Abstract: The present invention relates to a memory accessing circuit, which is for accessing a memory circuit with 2N impedance states. The memory accessing circuit includes a testing signal generating circuit, for generating a testing signal by detecting the impedance state of the memory circuit; a reference signal generating circuit, for generating 2N?1 reference signals by detecting the impedance states of a reference circuit having 2N?1 impedance paths; a median signal generating circuit, for generating (2N?1)?1, median signals by receiving the 2N?1 reference signals; and a comparing circuit, for comparing the testing signal and the (2N?1) median signals. The present invention further provides a memory accessing method thereof.

Abstract: A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level.

Abstract: The present invention relates to a memory accessing circuit, which is for accessing a memory circuit with 2N impedance states. The memory accessing circuit comprises a testing signal generating circuit, for generating a testing signal by detecting the impedance state of the memory circuit; a reference signal generating circuit, for generating 2N?1 reference signals by detecting the impedance states of a reference circuit having 2N?1 impedance paths; a median signal generating circuit, for generating (2N?1)?1, median signals by receiving the 2N?1 reference signals; and a comparing circuit, for comparing the testing signal and the (2N?1) median signals. The present invention further provides a memory accessing method thereof.

Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node. The source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes. The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.

Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell with changeable resistance and a plurality of reference cells. The first current mirror circuit, coupled to the output terminal of the memory cell, generates a second memory cell current at a first node according to a first memory cell current through the memory cell. The second current mirror circuit, coupled to the output terminal of the reference cells, generates a plurality of second reference currents at a plurality of second nodes according to a plurality of first reference currents through the reference cells. The load circuit, coupled to the first node, the second nodes, and a ground, provides equal loads for the second memory cell current and the second reference currents to respectively generate a memory cell voltage at the first node and a plurality of reference voltages at the second nodes.

Abstract: A method of fabricating of a metal line by a wet process is provided. A catalytic adhesive layer is formed on an insulating substrate. A fist metal layer is formed by an electoless plating process, and then, a second metal layer is formed by an electoless plating process or an electoplating process. The first and the second metal layers are patterned to form a metal line.

Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node. The source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes. The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.

Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell with changeable resistance and a plurality of reference cells. The first current mirror circuit, coupled to the output terminal of the memory cell, generates a second memory cell current at a first node according to a first memory cell current through the memory cell. The second current mirror circuit, coupled to the output terminal of the reference cells, generates a plurality of second reference currents at a plurality of second nodes according to a plurality of first reference currents through the reference cells. The load circuit, coupled to the first node, the second nodes, and a ground, provides equal loads for the second memory cell current and the second reference currents to respectively generate a memory cell voltage at the first node and a plurality of reference voltages at the second nodes.