Abstract: A display apparatus includes a base substrate including a display region and a peripheral region that is a non-display region surrounding the display region, a plurality of data lines disposed in the display region on the base substrate and extending to the peripheral region, a bypass data line disposed in the display region and the peripheral region on the base substrate and electrically connected to at least one of the data lines, and a dummy pattern spaced apart from the bypass data line and disposed on a same layer as the bypass data line.

Abstract: The present invention relates to an electrolyte solution and a secondary battery including the same. According to the present invention, the present invention has an effect of providing a secondary battery having improved charging efficiency and output due to low discharge resistance and having a long lifespan and excellent high-temperature capacity retention by suppressing gas generation and increase in thickness.

Abstract: The present invention relates to an electrolyte solution and a secondary battery including the same. According to the present invention, the present invention has an effect of providing a secondary battery having improved charging efficiency and output due to low discharge resistance and having a long lifespan and excellent high-temperature capacity retention by suppressing gas generation and increase in thickness.

Abstract: The present invention relates to an electrolyte solution and a secondary battery including the same. According to the present invention, the present invention has an effect of providing a secondary battery having improved charging efficiency and output due to low discharge resistance and having a long lifespan and excellent high-temperature capacity retention by suppressing gas generation and increase in thickness.

Abstract: The present invention relates to an electrolyte solution and a secondary battery including the same. According to the present invention, the present invention has an effect of providing a secondary battery having improved charging efficiency and output due to low discharge resistance and having a long lifespan and excellent high-temperature capacity retention by suppressing gas generation and increase in thickness.

Abstract: A display device includes a light-emitting diode including a first conductivity-type semiconductor, an active layer, and a second conductivity-type semiconductor; a first voltage line to which a first voltage is applied; a second voltage line to which a second voltage is applied; a first transistor including a source electrode electrically connected to the first voltage line and a drain electrode electrically connected to a first electrode of the light-emitting diode and to the first conductivity-type semiconductor; a second transistor including a drain electrode electrically connected to a gate electrode of the first transistor and a source electrode electrically connected to a data line to apply a data signal; a capacitor electrically connected to the gate electrode of the first transistor and the first electrode; and a third transistor including a source electrode electrically connected to the second voltage line and a drain electrode electrically connected to the first electrode.

Abstract: Disclosed is an organometallic precursor for forming a metal pattern, having a structure defined by the following Formula 1, and a method of forming the metal pattern using the same, in which the conductive metal pattern is readily formed through an exposing step without using a photo-resist.

Abstract: Disclosed is an organometallic precursor for forming a metal pattern, having a structure defined by the following Formula 1, and a method of forming the metal pattern using the same, in which the conductive metal pattern is readily formed through an exposing step without using a photo-resist.

Abstract: Disclosed is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks, a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks, a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed; said conjunction areas comprising one or more LA drivers adapted to drive block sense amplifiers, one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers, and-one or more BSYD circuits adapted to selectively enables LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining column and row block address decoding sign

Abstract: A semiconductor memory device and method for its operation are disclosed. The memory device uses refresh-type memory cells, but operates within the same timing parameters as an SRAM. A refreshing operation and a successful read/write operation can both be performed in a read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refreshing operations can also be performed during the read/write cycle. Thus the device operates with no maximum write cycle time limitation. In the disclosed method, an external write command causes the device to store the write address and data to registers instead of to the memory cell array. When the external write command signals that data is present, zero write recovery time is needed, since the registers require no address setup time. Because the memory cell array is not involved in this transaction, refresh operations can proceed as needed during the external write command, no matter how long the external write takes to complete.

Abstract: Disclosed is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks, a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks, a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed; said conjunction areas comprising one or more LA drivers adapted to drive block sense amplifiers, one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers, and one or more BSYD circuits adapted to selectively enables LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining column and row block address decoding sign

Abstract: A semiconductor memory device and method for its operation are disclosed. The memory device uses refresh-type memory cells, but operates within the same timing parameters as an SRAM. A refreshing operation and a successful read/write operation can both be performed in a read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refreshing operations can also be performed during the read/write cycle. Thus the device operates with no maximum write cycle time limitation.

Abstract: A semiconductor memory device and method for its operation are disclosed. The memory device uses refresh-type memory cells, but operates within the same timing parameters as a SRAM. A refreshing operation and a successful read/write operation can both be performed in a read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refreshing operations can also be performed during the read/write cycle. Thus the device operates with no maximum write cycle time limitation. In the disclosed method, an external write command causes the device to store the write address and data to registers instead of to the memory cell array. When the external write command signals that data is present, zero write recovery time is needed, since the registers require no address setup time. Because the memory cell array is not involved in this transaction, refresh operations can proceed as needed during the external write command, no matter how long the external write takes to complete.

Abstract: A self-resetting circuit includes a logic circuit operative to transition an output signal from a first logic state to a second logic state responsive to a first logic state transition of an input signal, along with a bistable reset circuit coupled to the logic circuit and operative to be triggered by the transition of the output signal from the first logic state to the second logic state to reset the output signal to the first logic state within a first predetermined interval following the transition of the output signal from the first logic state to the second logic state, and to be armed by a second logic state transition of the input signal next succeeding the first logic state transition, wherein the reset circuit is armed within a second predetermined interval following the second transition that is less than the first predetermined interval. Related operating methods are also discussed.

Abstract: The semiconductor memory device includes a memory cell array, sense amplifying means for generating a sense output signal pair, and a data output buffer for providing the sense output signal pair. The data output buffer includes a level shifter for generating a first data output signal pair by shifting the level of the sense output signal pair responsive to the output buffer enable signal. A register inverts and latches the first data output signal pair, generating a second data output signal pair. A first transmission and latch means transmits and latches the second data output signal pair generating a third data output signal pair responsive to a first control signal. A second transmission and latch means transmits and latches the second data output signal pair generating a fourth data output signal pair responsive to a second control signal. A first inverter generates a fifth data output signal pair by inverting the third data output signal pair responsive to a first data output control signal.

Abstract: A synchronous burst semiconductor memory device operating in synchronism with at least one external clock signal and capable of accessing data on every edge of the external clock signal is provided. The burst memory device includes a clock generator for generating a number of data output/input strobe clock signals synchronized with the external clock signal in response to a plurality of input information signals, and a data-out/in buffer for outputting/inputting internal/external data in synchronism with the data output/input strobe clock signals.

Abstract: Disclosed is a semiconductor memory device including a redundancy controller. The redundancy controller is structured using pass gate logic, dynamic inverter circuits, and a true/complement decoder scheme. The redundancy controller includes first and second redundancy enable circuits corresponding respectively to first and second redundant columns. A first and second fuse boxes are coupled respectively to the first and second redundancy enable circuits. The first and second fuse boxes each include a fuse box circuit corresponding to the column address signals and a fuse element. Each fuse box circuit receives a corresponding pair of true and complement column address signals and manipulates the true and complement column address signals responsive to the fuse element. A first decoding means decodes the manipulated versions of the true and complement column address signals and generates first and second true decoded pulse signals and first and second complement decoded pulse signals.

Abstract: Disclosed is a decoder circuit including: a redundancy section row decoder for responding a redundancy main word line signal, thereby selecting a redundancy section word line; a normal section row decoder for receiving a redundancy signal and a normal main word line signal applied from a row redundancy address decoder, thereby selecting a section word line; and, a row redundancy address decoder for generating a signal having a pulse width up to before a next cycle following a redundancy cycle as a redundancy signal, thereby providing the signal to the normal section row decoder and providing the redundancy main word line signal to the redundancy section row decoder during the redundancy cycle, in response to a clock transiting in the redundancy cycle.