Abstract: A semiconductor device includes a structure on a substrate and a plurality of gate-all-around devices on the structure. The structure includes a plurality of sacrificial layers and a plurality of active layers alternately stacked on one another. The sacrificial layers have different widths and the active layers have different widths to form multiple stepped layers on the substrate. The gate-all-around devices are on respective ones the multiple stepped layers.

Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Abstract: A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.

Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Abstract: A semiconductor device comprises a substrate extending in a horizontal direction and a vertical transistor on the substrate. The vertical transistor comprises: a first diffusion region on the substrate; a channel region on the first diffusion region and extending in a vertical direction relative to the horizontal direction of the extension of the substrate; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel region. A horizontal transistor is positioned on the substrate, the horizontal transistor comprising: a first diffusion region and a second diffusion region on the substrate and spaced apart from each other; a channel region on the substrate between the first diffusion region and the second diffusion region; and a gate electrode on the channel region and isolated from the channel region.

Abstract: A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.

Abstract: A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.

Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Abstract: A semiconductor device comprises a substrate extending in a horizontal direction and a vertical transistor on the substrate. The vertical transistor comprises: a first diffusion region on the substrate; a channel region on the first diffusion region and extending in a vertical direction relative to the horizontal direction of the extension of the substrate; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel region. A horizontal transistor is positioned on the substrate, the horizontal transistor comprising: a first diffusion region and a second diffusion region on the substrate and spaced apart from each other; a channel region on the substrate between the first diffusion region and the second diffusion region; and a gate electrode on the channel region and isolated from the channel region.

Abstract: In a semiconductor device, a vertical transistor comprises: a first diffusion region on a substrate; a channel region on the first diffusion region and extending in a vertical direction; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel region. A horizontal transistor is positioned on the substrate, the horizontal transistor comprising: a first diffusion region and a second diffusion region on the substrate and spaced apart from each other; a channel region on the substrate between the first diffusion region and the second diffusion region; and a gate electrode on the channel region and isolated from the channel region. A portion of a gate electrode of the vertical transistor and a portion of the gate electrode of the horizontal transistor are at a same vertical position in the vertical direction relative to the substrate.

Abstract: A back-bias region is disposed on a substrate. A buried insulating layer covers the substrate and the back-bias region. A body is formed on the buried insulating layer and partially overlaps the back-bias region. A drain is in contact with the body. A gate electrode covers top and lateral surfaces of the body.

Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Abstract: A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.

Abstract: A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate, aligned with the sidewalls, a silicide layer on the gate electrode, a silicide layer on the source/drain region, and second spacers covering the first spacers and end parts of a surface of the silicide layer on the source drain region.

Abstract: According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes forming a sacrificial pattern having SiGe on a crystalline silicon substrate. A body having crystalline silicon is formed on the sacrificial pattern. At least one active element is formed on the body. An insulating layer is formed to cover the sacrificial pattern, the body, and the active element. A contact hole is formed to expose the sacrificial pattern through the insulating layer. A void space is formed by removing the sacrificial pattern. An amorphous silicon layer is formed in the contact hole and the void space. The amorphous silicon layer is transformed into a metal silicide layer.

Abstract: According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes forming a sacrificial pattern having SiGe on a crystalline silicon substrate. A body having crystalline silicon is formed on the sacrificial pattern. At least one active element is formed on the body. An insulating layer is formed to cover the sacrificial pattern, the body, and the active element. A contact hole is formed to expose the sacrificial pattern through the insulating layer. A void space is formed by removing the sacrificial pattern. An amorphous silicon layer is formed in the contact hole and the void space. The amorphous silicon layer is transformed into a metal silicide layer.

Abstract: Methods of fabricating a semiconductor device, and related devices, include forming a gate electrode on a substrate, forming a first buffer layer, a second buffer layer and a third buffer layer on side surfaces of the gate electrode and on the substrate near the gate electrode, forming a spacer covering the side surfaces of the gate electrode on the third buffer layer, the third buffer layer on the substrate being exposed, exposing the second buffer layer on the substrate by removing the exposed third buffer layer, exposing the first buffer layer on the substrate by removing the exposed second buffer layer, forming deep junction in the substrate using the spacer as a mask, and removing the spacer. The third buffer layer is a material layer having a higher dielectric constant than the second buffer layer. The spacer includes a material layer different than the third, second and first buffer layers.

Abstract: Methods of fabricating a semiconductor device, and related devices, include forming a gate electrode on a substrate, forming a first buffer layer, a second buffer layer and a third buffer layer on side surfaces of the gate electrode and on the substrate near the gate electrode, forming a spacer covering the side surfaces of the gate electrode on the third buffer layer, the third buffer layer on the substrate being exposed, exposing the second buffer layer on the substrate by removing the exposed third buffer layer, exposing the first buffer layer on the substrate by removing the exposed second buffer layer, forming deep junction in the substrate using the spacer as a mask, and removing the spacer. The third buffer layer is a material layer having a higher dielectric constant than the second buffer layer. The spacer includes a material layer different than the third, second and first buffer layers.

Abstract: A back-bias region is disposed on a substrate. A buried insulating layer covers the substrate and the back-bias region. A body is formed on the buried insulating layer and partially overlaps the back-bias region. A drain is in contact with the body. A gate electrode covers top and lateral surfaces of the body.