Patents by Inventor Min-Chul Sung
Min-Chul Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230422514Abstract: A semiconductor device includes: a first common plate extending vertically in a first direction; a second common plate which is spaced apart from the first common plate in a second direction and extends vertically in the first direction; a slit formed between the first common plate and the second common plate; a first memory cell array sharing the first common plate and including first capacitors that are vertically stacked in the first direction; and a second memory cell array sharing the second common plate and including second capacitors that are vertically stacked in the first direction.Type: ApplicationFiled: November 30, 2022Publication date: December 28, 2023Inventor: Min Chul SUNG
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Publication number: 20230017800Abstract: A semiconductor device includes a plurality of bit line structures formed to be spaced apart from each other over a semiconductor substrate, a first spacer formed on both sidewalls of each of the bit line structures, a lower plug formed between the bit line structures and in contact with the semiconductor substrate, an upper plug positioned over the lower plug and having a greater line width than the lower plug, a middle plug positioned between the lower plug and the upper plug and having a smaller line width than a line width of the lower plug, and a second spacer positioned between the middle plug and the first spacer, wherein the second spacer is thicker than the first spacer.Type: ApplicationFiled: April 11, 2022Publication date: January 19, 2023Inventor: Min Chul SUNG
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Patent number: 10650219Abstract: According to various example embodiments, an electronic device is disclosed. The electronic device includes a housing having a first surface facing a first direction and a second surface facing a second, opposing direction. A first area of the first surface includes a plurality of selectable input keys. A second area of the first surface excludes the plurality of keys. A sensor module, such as a fingerprint sensor, is installed to the first area.Type: GrantFiled: November 16, 2017Date of Patent: May 12, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hwanmyung Noh, Young-Gwon Koo, Taewan Kim, Min-Chul Sung, Seungwoon Lee
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Publication number: 20180165493Abstract: According to various example embodiments, an electronic device is disclosed. The electronic device includes a housing having a first surface facing a first direction and a second surface facing a second, opposing direction. A first area of the first surface includes a plurality of selectable input keys. A second area of the first surface excludes the plurality of keys. A sensor module, such as a fingerprint sensor, is installed to the first area.Type: ApplicationFiled: November 16, 2017Publication date: June 14, 2018Inventors: Hwanmyung NOH, Young-Gwon KOO, Taewan KIM, Min-Chul SUNG, Seungwoon LEE
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Patent number: 9472644Abstract: A method for fabricating a semiconductor device includes forming a gate structure over a substrate, forming a multi-layer sidewall spacer including a first sacrificial spacer which covers sidewalls of the gate structure and a second sacrificial spacer which is disposed on a sidewall of the first sacrificial spacer and recessed lower than an upper surface of the gate structure, forming an air gap having a narrower width top portion than a middle and a bottom portions, by removing the first and second sacrificial spacers, and forming a capping layer which caps the top portion of the air gap.Type: GrantFiled: July 17, 2014Date of Patent: October 18, 2016Assignee: SK Hynix Inc.Inventor: Min-Chul Sung
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Patent number: 9443860Abstract: An e-fuse including a substrate including a first active region and a second active region which are spaced from each other by an isolation region, a first program gate and a second program gate which are disposed over the first active region in parallel with each other, a single select gate disposed over the second active region; a sharing doping region formed in the first active region between the first program gate and the second program gate, a first doping region and a second doping region that are formed in the second active region on both sides of the select gate, a first metal line suitable for electrically coupling the sharing doping region to the first doping region and a second metal line connected to the second doping region.Type: GrantFiled: September 23, 2015Date of Patent: September 13, 2016Assignee: SK Hynix Inc.Inventor: Min-Chul Sung
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Patent number: 9257345Abstract: An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.Type: GrantFiled: March 4, 2015Date of Patent: February 9, 2016Assignee: SK HYNIX INC.Inventor: Min Chul Sung
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Patent number: 9230793Abstract: A semiconductor device has a semiconductor substrate including a cell region and a peripheral region and includes: a Silicon-Metal-Silicon (SMS)-structured wafer formed in the cell region, which includes a stacked structure of a first silicon substrate, a metal layer, and a second silicon substrate; and a Silicon On Insulator (SOI)-structured wafer formed in the peripheral region, which includes a stacked structure of the first silicon substrate, a silicon insulation film, and the second silicon substrate.Type: GrantFiled: March 4, 2014Date of Patent: January 5, 2016Assignee: SK HYNIX INC.Inventor: Min Chul Sung
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Publication number: 20150228754Abstract: A method for fabricating a semiconductor device includes forming a gate structure over a substrate, forming a multi-layer sidewall spacer including a first sacrificial spacer which covers sidewalls of the gate structure and a second sacrificial spacer which is disposed on a sidewall of the first sacrificial spacer and recessed lower than an upper surface of the gate structure, forming an air gap having a narrower width top portion than a middle and a bottom portions, by removing the first and second sacrificial spacers, and forming a capping layer which caps the top portion of the air gap.Type: ApplicationFiled: July 17, 2014Publication date: August 13, 2015Inventor: Min-Chul SUNG
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Publication number: 20150179526Abstract: An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.Type: ApplicationFiled: March 4, 2015Publication date: June 25, 2015Inventor: Min Chul SUNG
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Publication number: 20150108574Abstract: A semiconductor device has a semiconductor substrate including a cell region and a peripheral region and includes: a Silicon-Metal-Silicon (SMS)-structured wafer formed in the cell region, which includes a stacked structure of a first silicon substrate, a metal layer, and a second silicon substrate; and a Silicon On Insulator (SOI)-structured wafer formed in the peripheral region, which includes a stacked structure of the first silicon substrate, a silicon insulation film, and the second silicon substrate.Type: ApplicationFiled: March 4, 2014Publication date: April 23, 2015Applicant: SK HYNIX INC.Inventor: Min Chul SUNG
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Patent number: 9000560Abstract: An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.Type: GrantFiled: March 15, 2013Date of Patent: April 7, 2015Assignee: SK Hynix Inc.Inventor: Min Chul Sung
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Patent number: 8993391Abstract: A method for fabricating a semiconductor device includes forming a conductive layer over first and second regions of a semiconductor substrate, forming a trench extended in the first region of the semiconductor substrate through the conductive layer, forming a recessed gate electrode in the trench, doping the conductive layer and the recessed first gate electrode, and forming a second gate electrode by etching the doped conductive layer.Type: GrantFiled: March 16, 2013Date of Patent: March 31, 2015Assignee: SK Hynix Inc.Inventor: Min-Chul Sung
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Publication number: 20140183689Abstract: An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.Type: ApplicationFiled: March 15, 2013Publication date: July 3, 2014Applicant: SK HYNIX INC.Inventor: Min Chul SUNG
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Publication number: 20140187031Abstract: A method for fabricating a semiconductor device includes forming a conductive layer over first and second regions of a semiconductor substrate, forming a trench extended in the first region of the semiconductor substrate through the conductive layer, forming a recessed gate electrode in the trench, doping the conductive layer and the recessed first gate electrode, and forming a second gate electrode by etching the doped conductive layer.Type: ApplicationFiled: March 16, 2013Publication date: July 3, 2014Applicant: SK hynix Inc.Inventor: Min-Chul SUNG
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Patent number: 8766333Abstract: A semiconductor device includes a first buried bit line (120a) provided between lower and upper substrates (100b, 100a), first and second pillar patterns (105a, 105b) extending from the upper substrate (100a) and coupled to the first buried bit line (120a) through first and second gate patterns (140a), respectively. A first body contact pattern (160a) coupled to the first and/or the second pillar patterns (105a, 105b) through the upper substrate (100a) prevents the first and the second pillar patterns from floating.Type: GrantFiled: December 14, 2011Date of Patent: July 1, 2014Assignee: Hynix Semiconductor Inc.Inventor: Min Chul Sung
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Patent number: 8357969Abstract: A semiconductor device having a vertical channel transistor and a method for manufacturing the same are provided. In the semiconductor device, a metal bit line is formed between vertical channel transistors, and the metal bit line is connected to only one of the vertical channel transistors through an asymmetric bit line contact. Through such a structure, the resistance of the bit line can be improved and the process margin for formation of the bit line can be secured.Type: GrantFiled: June 30, 2009Date of Patent: January 22, 2013Assignee: Hynix Semiconductor IncInventor: Min Chul Sung
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Publication number: 20120153365Abstract: A semiconductor device includes a first buried bit line (120a) provided between lower and upper substrates (100b, 100a), first and second pillar patterns (105a, 105b) extending from the upper substrate (100a) and coupled to the first buried bit line (120a) through first and second gate patterns (140a), respectively. A first body contact pattern (160a) coupled to the first and/or the second pillar patterns (105a, 105b) through the upper substrate (100a) prevents the first and the second pillar patterns from floating.Type: ApplicationFiled: December 14, 2011Publication date: June 21, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Min Chul SUNG
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Patent number: 8063117Abstract: The present invention relates to an artificial marble comprising a base resin part; and a pearl stripe part which contains a matrix resin and pearls, and expresses stripes on said base resin part by the contained pearls and a process for preparing the same. The present invention may provide an artificial marble, which can embody higher grade appearance effects by concentrating pearl into the parts expressing stripes of the artificial marble and freely regulating color, quality of pearl and/or patterns of stripes, and a process for preparing the same.Type: GrantFiled: January 8, 2008Date of Patent: November 22, 2011Assignee: LG Chem, Ltd.Inventor: Min Chul Sung
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Publication number: 20110186970Abstract: A method for manufacturing a semiconductor device comprises: etching a semiconductor substrate to form a plurality of pillars; depositing a first protective film on the sidewalls of the pillar; first etching the semiconductor substrate with the pillar deposited with the first protective film as a mask; forming a first insulating film on the sidewalls of the pillar and the first etched semiconductor substrate; second etching the semiconductor substrate with the pillar including the first insulating film as a mask; forming a second protective film and a second insulating film on the surface of the second etched semiconductor substrate; depositing a barrier film on the sidewalls of the pillar including the second insulating film; and removing the first insulating film, the second insulating film and the barrier film disposed at one sidewall of the pillar to form a contact hole defined by the first protective film and the second protective film.Type: ApplicationFiled: July 20, 2010Publication date: August 4, 2011Applicant: Hynix Semiconductor Inc.Inventor: Min Chul SUNG