Abstract: The techniques of the disclosure are directed to reducing power consumption in a device through adaptive backlight level (ABL) scaling. The techniques may utilize a temporal approach in implementing the ABL scaling to adjust the backlight level of a display for a current video frame in a sequence of video frames presented on the display. The techniques may include receiving an initial backlight level adjustment for the current video frame and determining whether to adjust the backlight level adjustment for the current video frame based on a historical trend. The techniques may also determine the historical trend of backlight level adjustments between the current video frame and one or more preceding video frames in the sequence.

Abstract: A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH3); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.

Abstract: Systems and methods for performing X-ray Photoelectron Spectroscopy (XPS) measurements in a semiconductor environment are disclosed. A reference element peak is selected and tracked as part of the measurement process. Peak shift of the reference element peak, in electron volts (eV) is tracked and applied to other portions of acquired spectrum to compensate for the shift, which results from surface charge fluctuation.

Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

Abstract: A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.

Abstract: A decoder may apply a resource-focused interpolation mode to enable or disable interpolation or extrapolation of video units, such as frames, based on power and quality considerations. In one mode, interpolation may be disabled to conserve power when reference frames are not likely to produce satisfactory quality. In another mode, the threshold may be adjustable as a function of power saving requirements. This disclosure also describes selection of reference video frames to be used for interpolation or extrapolation of a video frame. A decoder may apply a quality-focused mode to select a reference frame based on quality criteria. The quality criteria may indicate a level of quality likely to be produced by a reference frame. If no reference frames satisfy the quality criteria, interpolation or extrapolation may be disabled. Display of an interpolated or extrapolated frame may be selectively enabled based on a quality analysis of the frame.

Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

Abstract: A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

Abstract: A method for vertically grounding and leading down form a center of a composite pole tower includes the following steps: extending a ground down-leading wire from a center of a ground wire cross arm which is made of metal and is positioned on top of the pole tower, wherein the ground down-leading wire is vertically leaded down to the earth form the center of the composite pole tower, wherein when an lower portion of the tower body is a metal pipe, the ground down-leading wire is extended from the center of the composite material and is directly connected to the metal pipe. The method utilizes the advantage of the insulating intensity of the wall of the composite pole tower and enhances the insulating intensity of the transmission line on impact of lightning. The ground down-leading wires are prevented from short-circuiting with the tower body of the composite pole tower, so that advantage of the insulating property of the composite material of the pole towers is realized.

Abstract: Systems and methods for performing X-ray Photoelectron Spectroscopy (XPS) measurements in a semiconductor environment are disclosed. A reference element peak is selected and tracked as part of the measurement process. Peak shift of the reference element peak, in electron volts (eV) is tracked and applied to other portions of acquired spectrum to compensate for the shift, which results from surface charge fluctuation.

Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

Abstract: A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.

Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

Abstract: Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.

Abstract: A method for vertically grounding and leading down form an outer side of a composite pole tower and pole tower thereof, wherein the method includes the following steps: extending an upper metal cross arm from an extended line of at least one side of a ground wire cross arm, vertically leading down a ground down-leading wire from a distal end of the upper metal cross arm, connecting the ground down-leading wire to the pole tower via a lower metal cross arm at a distance under a lower lead, and grounding the ground down-leading wire along a tower body of the pole tower, wherein when an lower portion of the tower body is a metal pipe, the ground down-leading wire is selectively directly connected to the metal pipe via the lower metal cross arm.

Abstract: A method for vertically grounding and leading down form an inner side of a composite pole tower and pole tower thereof, wherein the method includes the following steps: extending an upper metal cross arm from an extended line of at least one side of a ground wire cross arm which is made of metal, vertically leading down a ground down-leading wire from a distal end of the upper metal cross arm, connecting the ground down-leading wire to the pole tower via a lower metal cross arm at a distance under a lower lead, and grounding the ground down-leading wire along a tower body of the pole tower, wherein when an lower portion of the tower body is a metal pipe, the ground down-leading wire is selectively directly connected to the metal pipe via the lower metal cross arm. The upper metal cross arm and the lower cross arm are able to provide a distance between the ground down-leading wire and the pole tower.

Abstract: A system and method generate atomic hydrogen (H) for deposition of a pure metal in a three-dimensional (3D) structure. The method includes forming a monolayer of a compound that includes the pure metal. The method also includes depositing the monolayer on the 3D structure and immersing the 3D structure with the monolayer in an electrochemical cell chamber including an electrolyte. Applying a negative bias voltage to the 3D structure with the monolayer and a positive bias voltage to a counter electrode generates atomic hydrogen from the electrolyte and deposits the pure metal from the monolayer in the 3D structure.

Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

Abstract: Methods and systems are provided for assessing a vehicle transmission having a resolver. A memory is configured to store preliminary data pertaining to an error of the resolver. A processor is coupled to the memory, and is configured to determine a harmonic characteristic of the preliminary data, and to assess the vehicle transmission using the harmonic characteristic.

Abstract: A method of forming a dielectric stack devoid of an interfacial layer includes subjecting an exposed interfacial layer provided on a semiconductor material to a low pressure thermal anneal process for a predetermined time period at a temperature of about 900° C. to about 1000° C. with an inert gas purge. A semiconductor structure is also disclosed, with a dielectric stack devoid of an interfacial layer.