Abstract: A system selecting a process key factor in a commercial chemical process, includes: a data extraction unit that extracts tag data in units of a set period; an outlier discrimination unit that discriminates and aggregates outliers by tag by using an outlier extraction reference master; an outlier processing unit that generates an input mart draft excluding the outliers; a derived variable generation unit that generates derived variables for each tag, and generates an advanced input mart having the derived variable added thereto; a yield calculation unit that backs up the result of calculation of a yield by realizing a target value via exclusion and correction of the outliers; and a key factor extraction unit that extracts a yield key factor by calculating importance of each tag, and backs up importance data for each tag.

Abstract: A system for predicting process changes by using key factors in a commercial chemical process, includes: a key factor extraction and individual tag importance backup unit that extracts yield key factors by calculating the importance of each tag, and backs up importance data for each tag; and a yield prediction model training and yield prediction performing unit that performs yield prediction model training by using the importance of each tag accumulated in the key factor extraction and individual tag importance backup unit, and performs yield prediction so as to output a yield prediction result, evaluates performance, and selects an optimal prediction model.

Abstract: The present disclosure relates to an organic compound having the following structure of Formula 1, an organic light emitting diode (OLED) where an electron transport layer and/or a charge generation layer includes the organic compound and an organic light emitting device including the organic light emitting diode. While only the specific moiety in the organic compound is deuterated, the organic compound can implement excellent luminous efficiency and luminous lifespan as a compound where all the carbon atoms are deuterated. The OLED can maximize its luminous efficiency and luminous lifespan with minimizing utilization of expensive deuterium.

Abstract: The present disclosure relates to an organic compound, and an organic light emitting diode and an organic light emitting device including the same, more specifically, relates to an organic compound being represented by following Formula, an organic light emitting diode including the organic compound and an organic light emitting device including the organic light emitting diode. The organic compound is included in an electron transporting layer and/or a p-type charge generation layer of the organic light emitting diode.

Abstract: A semiconductor device package-on-package (PoP) includes a first package, a second package, an interposer, a first molding layer, and a second molding layer. The first package includes a first substrate and a first semiconductor chip on the first substrate. The second package is disposed on the first package and includes a second substrate and a second semiconductor chip on the second substrate. The interposer is disposed between the first package and the second package and connects the first package and the second package. A first molding layer fills a space between the first package and the interposer. A second molding layer covers an upper surface of the interposer.

Abstract: A semiconductor device package-on-package (PoP) includes a first package, a second package, an interposer, a first molding layer, and a second molding layer. The first package includes a first substrate and a first semiconductor chip on the first substrate. The second package is disposed on the first package and includes a second substrate and a second semiconductor chip on the second substrate. The interposer is disposed between the first package and the second package and connects the first package and the second package. A first molding layer fills a space between the first package and the interposer. A second molding layer covers an upper surface of the interposer.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a first semiconductor chip that is on the substrate. The first semiconductor chip includes a first surface facing the substrate, a second surface opposite the first surface and having a first circuit region therein, and a first TSV extending between the first surface and the second surface. An upper semiconductor chip is on the second surface of the first semiconductor chip, is electrically connected with the first semiconductor chip, includes an upper circuit region in a surface thereof facing the second surface of the first semiconductor chip, and does not have a TSV extending through an inside thereof. A thickness of the upper semiconductor chip is greater than a thickness of the first semiconductor chip.

Abstract: A semiconductor memory device includes a program and read unit suitable for programming program data in a memory cell array and for reading read data stored in the memory cell array, and a control unit suitable for generating a control signal for controlling the program and read unit in response to a command input from the outside of the semiconductor memory device, in which the control unit controls the program and read unit to read the read data in a state of storing a first bit data of the program data when a read command is input while programming the program data.

Abstract: A semiconductor memory device includes a program and read unit suitable for programming program data in a memory cell array and for reading read data stored in the memory cell array, and a control unit suitable for generating a control signal for controlling the program and read unit in response to a command input from the outside of the semiconductor memory device, in which the control unit controls the program and read unit to read the read data in a state of storing a first bit data of the program data when a read command is input while programming the program data.

Abstract: A semiconductor memory device includes a program and read unit suitable for programming program data in a memory cell array and for reading read data stored in the memory cell array, and a control unit suitable for generating a control signal for controlling the program and read unit in response to a command input from the outside of the semiconductor memory device, in which the control unit controls the program and read unit to read the read data in a state of storing a first bit data of the program data when a read command is input while programming the program data.

Abstract: A semiconductor memory device includes a program and read unit suitable for programming program data in a memory cell array and for reading read data stored in the memory cell array, and a control unit suitable for generating a control signal for controlling the program and read unit in response to a command input from the outside of the semiconductor memory device, in which the control unit controls the program and read unit to read the read data in a state of storing a first bit data of the program data when a read command is input while programming the program data.

Abstract: Provided is a semiconductor package in which a cell array region and a peripheral circuit region are formed as different semiconductor chips, respectively. First semiconductor chips including memory cells and a second semiconductor chip including only peripheral circuitry common to the first semiconductor chips are electrically connected to each other. Thus, a loading capacitance of the semiconductor package may be reduced. As a result, an RC delay of the semiconductor package may be reduced, thereby improving an operating speed of the semiconductor package.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. A method may include preparing a wiring board including a mounting region and a molding region surrounding the mounting region; forming a through-hole penetrating through the wiring board at the mounting region; mounting a semiconductor chip on the mounting region of the wiring board by a flip chip bonding method; and forming a molding covering the molding region of the wiring board and the semiconductor chip and filling the through-hole and a space between the semiconductor chip and the wiring board. The wiring board may have a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. A portion of the molding filling the through-hole has a surface coplanar with the second surface of the wiring board.

Abstract: Provided is a semiconductor package in which a cell array region and a peripheral circuit region are formed as different semiconductor chips, respectively. First semiconductor chips including memory cells and a second semiconductor chip including only peripheral circuitry common to the first semiconductor chips are electrically connected to each other. Thus, a loading capacitance of the semiconductor package may be reduced. As a result, an RC delay of the semiconductor package may be reduced, thereby improving an operating speed of the semiconductor package.

Abstract: A semiconductor memory device includes a program and read unit suitable for programming program data in a memory cell array and for reading read data stored in the memory cell array, and a control unit suitable for generating a control signal for controlling the program and read unit in response to a command input from the outside of the semiconductor memory device, in which the control unit controls the program and read unit to read the read data in a state of storing a first bit data of the program data when a read command is input while programming the program data.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. A method may include preparing a wiring board including a mounting region and a molding region surrounding the mounting region; forming a through-hole penetrating through the wiring board at the mounting region; mounting a semiconductor chip on the mounting region of the wiring board by a flip chip bonding method; and forming a molding covering the molding region of the wiring board and the semiconductor chip and filling the through-hole and a space between the semiconductor chip and the wiring board. The wiring board may have a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. A portion of the molding filling the through-hole has a surface coplanar with the second surface of the wiring board.

Abstract: An integrated circuit substrate includes an integrated circuit chip having a plurality of electrically conductive pads on a surface thereof and a printed circuit board mounted to the integrated circuit chip. The printed circuit board includes an alternating arrangement of first and second electrically conductive bond fingers. These first and second bond fingers are elevated at first and second different heights, respectively, relative to the plurality of electrically conductive pads. The printed circuit board also includes a first plurality of electrically insulating pedestals supporting respective ones of the first electrically conductive bond fingers at elevated heights relative to the second electrically conductive bond fingers. First and second pluralities of electrical interconnects (e.g., wires, beam leads) are also provided.

Abstract: An integrated circuit substrate includes an integrated circuit chip having a plurality of electrically conductive pads on a surface thereof and a printed circuit board mounted to the integrated circuit chip. The printed circuit board includes an alternating arrangement of first and second electrically conductive bond fingers. These first and second bond fingers are elevated at first and second different heights, respectively, relative to the plurality of electrically conductive pads. The printed circuit board also includes a first plurality of electrically insulating pedestals supporting respective ones of the first electrically conductive bond fingers at elevated heights relative to the second electrically conductive bond fingers. First and second pluralities of electrical interconnects (e.g., wires, beam leads) are also provided.