Abstract: There is provided a multilayer ceramic electronic component including a ceramic body including a plurality dielectric layers stacked thereon, a plurality of internal electrodes formed to be exposed to both end surface of the ceramic body, having the dielectric layer interposed therebetween, and external electrodes formed on the end surfaces of the ceramic body and electrically connected to the internal electrodes, respectively, wherein connectivity of the internal electrode is equal to or greater than 87%.

Abstract: A multilayer ceramic electronic component includes: a ceramic body including a recess portion formed in a length direction of at least one main surface thereof so as to be inwardly concave and satisfying T (thickness)/W (width)>1.0; first and second internal electrodes disposed to face each other in the ceramic body; and first and second external electrodes extended from the end surfaces of the ceramic body to the at least one main surface, wherein when the ceramic body is divided into an upper region At, corresponding to 70% to 90% of an overall thickness of the ceramic body, and a lower region Ab, corresponding to 10% to 30% of the overall thickness of the ceramic body, a ratio of an average particle size of Ab materials to an average particle size of At materials is less than 0.5.

Abstract: A multilayer ceramic electronic component includes a ceramic body including dielectric layers stacked in a thickness direction and satisfying T/W>1.0 when a width thereof is W and a thickness thereof is T; first and second internal electrodes; and first and second external electrodes, wherein when the ceramic body is divided into five regions in a width direction and a central region among the five regions is CW1 and regions adjacent to the central region CW1 are CW2 and CW3, a difference between electrode connectivity of the central region CW1 and electrode connectivity of the region CW2 or CW3 satisfies 0.02?(CW2 or CW3)?CW1?0.10.

Abstract: There are provided a multilayer ceramic electronic component and a manufacturing method thereof, such that a high capacitance multilayer ceramic electronic component having excellent reliability through the suppression of crack generation due to a step portion and an increase in an overlapped area may be provided.

Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body having a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated; wherein each internal electrode layer has a width gradually decreases from a center thereof towards both ends thereof in a length direction; and when a width of each internal electrode layer at the ends thereof in the length direction is defined as a minimum width L2 and a width of a portion of a margin portion M in each dielectric layer is defined as a maximum width M2, the portion of the margin portion M having no internal electrode layer present thereon and corresponding to the ends of each internal electrode layer in the length direction, a ratio of M2 to L2 (M2/L2) ranges from 0.2 to 0.3.

Abstract: There is provided a multilayer ceramic electronic component, including a ceramic body, and an internal electrode formed in the ceramic body and having a plurality of non-electrode regions formed therein, wherein in a cross section formed in length and thickness directions of the ceramic body, when a thickness of the internal electrode is Te, an area of the internal electrode is Ae, and an area of the plurality of non-electrode regions is Ao, 0.1 ?m?Te?0.55 ?m and 3.2%?Ao:Ae?4.5% are satisfied.

Abstract: A multilayer ceramic capacitor includes a ceramic body having first and second main surfaces opposing one another, first and second lateral surfaces opposing one another, and first and second end surfaces opposing one another. First and second internal electrodes have an overlap region with lead out portions exposed to the first lateral surface of the ceramic body. An insulating layer is formed to cover the overlap region of the lead out portions exposed to the first lateral surface of the ceramic body; and first and second external electrodes are formed on the first lateral surface of the ceramic body on which the insulating layer is formed and electrically connected to the first and second internal electrodes. Thicknesses of the insulating layer from the first lateral surface and the first and second external electrodes from the first lateral surface are specified.

Abstract: A multilayer ceramic electronic component including: a ceramic main body including a dielectric layer and having first and second main surfaces opposing one another, first and second lateral surfaces opposing one another, and first and second end surfaces opposing one another; a first internal electrode formed within the ceramic main body, including a capacitance formation part having an overlap region to form capacitance and a first lead out portion extending from the capacitance formation part so as to be exposed to the first lateral surface; a second internal electrode alternately laminated together with the first internal electrode, having a second lead out portion extending from the capacitance formation part so as to be exposed to the first lateral surface; first and second external electrodes; and insulating layers.

Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body having a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated; wherein each internal electrode layer has a width gradually decreases from a center thereof towards both ends thereof in a length direction; and when a width of each internal electrode layer at the ends thereof in the length direction is defined as a minimum width L2 and a width of a portion of a margin portion M in each dielectric layer is defined as a maximum width M2, the portion of the margin portion M having no internal electrode layer present thereon and corresponding to the ends of each internal electrode layer in the length direction, a ratio of M2 to L2 (M2/L2) ranges from 0.2 to 0.3.

Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body having a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated; wherein each internal electrode layer has a width gradually decreases from a center thereof towards both ends thereof in a length direction; and when a width of each internal electrode layer at the ends thereof in the length direction is defined as a minimum width L2 and a width of a portion of a margin portion M in each dielectric layer is defined as a maximum width M2, the portion of the margin portion M having no internal electrode layer present thereon and corresponding to the ends of each internal electrode layer in the length direction, a ratio of M2 to L2 (M2/L2) ranges from 0.2 to 0.3.

Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body having a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated; wherein each internal electrode layer has a width gradually decreases from a center thereof towards both ends thereof in a length direction; and when a width of each internal electrode layer at the ends thereof in the length direction is defined as a minimum width L2 and a width of a portion of a margin portion M in each dielectric layer is defined as a maximum width M2, the portion of the margin portion M having no internal electrode layer present thereon and corresponding to the ends of each internal electrode layer in the length direction, a ratio of M2 to L2 (M2/L2) ranges from 0.2 to 0.3.

Abstract: A method for fabricating a flash memory device includes forming device isolation films in a semiconductor substrate, defining active regions between the device isolation films, and patterning floating gates on the semiconductor substrate to correspond to the active regions. Portions where the active regions and the floating gates are not overlap with one another are within reference offset ranges, respectively.

Abstract: A method of manufacturing a semiconductor device including at leasty one of the following steps: sequentially forming a first oxide layer, a nitride layer, a second oxide layer, a bottom anti-reflect coating and a photo-resist pattern over a semiconductor substrate; exposing the uppermost surface of the semiconductor substrate by performing a first reactive ion etch process; and then forming a trench in the uppermost surface of the semiconductor substrate by performing a second reactive ion etch process.