Abstract: A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and is formed on the substrate and extends in a direction away from a major surface of the substrate. The first hard mask layer pattern is formed on a distal surface of the active fin from the substrate. The gate insulation layer is formed on a sidewall portion of the active fin. The first conductive layer pattern includes a metal silicide and is formed on surfaces of the substrate and the gate insulation layer pattern, and on a sidewall of the first hard mask pattern. The source/drain regions are formed in the active fin on opposite sides of the first conductive layer pattern.

Abstract: An image measuring apparatus for enhancing an accuracy of an image captured by an optical system and a method thereof are disclosed. The apparatus includes a CCD camera for capturing the object and outputting the captured image, a lamp for generating white light to illuminate a capturing area of the object, an illumination controller for controlling the lamp to be turned on, a piezoelectric actuator for controlling a minute height of the optical system with respect to the object, an image capturing device for acquiring the image captured by the CCD camera, a driving signal generator for outputting a driving signal to the illumination controller and the piezoelectric actuator when an enable signal is generated from the CCD camera, and an image signal processor for estimating height information of the object from data transmitted from the image capturing unit.

Abstract: An optically active element, such as a photonic crystal, is formed by creating a matrix (1) in which an optically active material is dispersed, and generating one or more void structures (2, 3) in the matrix. The matrix (1) may comprise polymer dispersed liquid crystal. The void structures (2, 3) may be generated by laser ablation. Properties of the optically active element may be tuned by thermal effects, or via the application of electric, magnetic, or polarised electromagnetic fields. The element may be adapted for use in beam steering, fluid detection, tunable lasers, polarisation multiplexing, and optical switching.

Abstract: The driving apparatus of a display device calculates a slope using a minimum gray, a maximum gray, a gray average of frame data in a current frame, and a gray average of frame data in a previous frame, and corrects and outputs the input frame data according to the slope, using frame data of one frame. As a result, a gray range of the input image signal can be extended, thereby improving visibility. Further, in a case of a motion picture, even when a difference of a gray range of images of adjacent frames is large, an original image is not distorted due to extension of a gray range. Also, even when noise is included in the input image signal, a gray range can be extended after removing the noise.

Abstract: An imaging system including a multi-mode fiber and a gradient index (GRIN) lens. The invention also relates to a system including a multi-mode fibre, such as a double-clad photonic crystal fibre, for transmitting an excitation signal to a sample for the purpose of imaging, and a scanning mechanism, which preferably includes a microelectromechanical system (MEMS) mirror, for reflecting the excitation signal in varying directions in order to scan the sample.

Abstract: The invention relates to materials and devices including these materials which have three-dimensional optical data storage capabilities, as well as to related methods and apparatus for storage, reading and erasing optical data. In particular, the invention relates to a three-dimensional optical data storage device comprising a data storage material which comprises a polymer matrix and nematic liquid crystal droplets wherein the nematic liquid crystal droplets are dispersed through the polymer matrix.

Abstract: There is provided a multilayer type test board assembly for high-precision inspection. The multilayer test board assembly comprises: a plurality of test boards separated from each other according to their functions, having input/output signal terminals, and including at least one test board each having a first section where first mounting devices sensitive to an influence of electrical signals are mounted and a second section where second mounting devices insensitive to an influence of electrical signals are mounted; spacers that arrange the test boards in parallel by spacing apart the test boards by predetermined intervals; connection cables connected to the input/output signal terminals of the test boards; and a signal shielding fence formed on each of the at least one test board so as to protect the first mounting devices from electrical signals generated by the second mounting devices.

Abstract: A system and method for testing a semiconductor integrated circuit (IC) in parallel includes a probe chuck, a test head, and a test controller. The probe chuck loads a plurality of different types of semiconductor DUTs. The test head provides a plurality of circuit sites to independently and simultaneously test the different types of semiconductor DUTs, and the test controller controls the test head and the probe chuck.

Abstract: In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern.

Abstract: In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern.

Abstract: A transferring system to travel along a rail to transfer and load and/or unload a workpiece include a transferring apparatus provided with a main body unit to travel along the rail, a sliding unit coupled to the main body unit to relatively move between a transferring position and a storing position with respect to the main body unit, and a hoist unit coupled to the sliding unit to move upward and downward the workpiece, and one or more buffering apparatus disposed beside a traveling path of the transferring apparatus to support the workpiece in the storing position, and provided with a supporting part to support the sliding unit when the sliding unit moves between the transferring position and the storing position.

Abstract: A probe card capable of multi-probing includes a print circuit board having a plurality of contact portions and a test module having a plurality of test boards. Each of the test boards includes at least one probing portion on which a plurality of needles are arrayed. The test module selects one of the test boards and probes semiconductor chips formed on a semiconductor wafer through the needles arrayed on the probing portion of the selected test board.

Abstract: A method for growing an epitaxial layer includes obtaining a semiconductor substrate having a plurality of insulating and conductive surfaces, adsorbing a first source gas into the plurality of conductive surfaces to grow a first epitaxial layer thereon, such that the first epitaxial layer has lateral portions overhanging the insulating surfaces, etching the first epitaxial layer to form an etched epitaxial layer, such that the etched epitaxial layer has curved surfaces, and supplying a second source gas to trigger additional epitaxial growth in the etched epitaxial layer.

Abstract: Methods of manufacturing a field effect transistor include forming a gate pattern on a substrate. A gate spacer is formed on a sidewall of the gate pattern. A first layer is formed from a surface of the substrate and contacting the gate spacer using a first selective epitaxial growth (SEG) process at a first temperature. A second layer is formed from a surface of the first layer and contacting the gate spacer using a second SEG process at a second temperature. The second temperature is lower than the first temperature. The first and second layers define elevated source/drain regions.

Abstract: A video processing apparatus, comprises a signal receiving part receiving a video signal through one of a plurality of channels, a user inputting part in which the channel is selected and inputted by a user, a video processing part processing the video signal received by the signal receiving part, and a controller controlling the signal receiving part to start receiving a video signal through a first channel upon the first channel selection among the plurality of channels by the user, and to start receiving a video signal through a second channel upon the second channel selection among the plurality of channels by the user, wherein the second channel selection is made during the receiving process of the first channel. Thus, the present invention provides a video processing apparatus and a video processing method capable of performing a channel change rapidly to solve the above-described problem.

Abstract: A satellite broadcast receiver comprises an antenna, a tuner, a modulator, a FEC decoder, a microprocessor, and an antenna driver. The antenna receives the satellite signal and the tuner tunes the satellite signal received by the antenna, and the modulator modulates the satellite signal tuned by the tuner into digital signal, the FEC decoder corrects a position error of the satellite antenna using the signal modulated by the modulator, and outputs a corresponding output signal, and the microprocessor receives the signal modulated by the modulator and the output signal of the error corrector, and outputs a control signal which controls the position of the antenna, and the antenna driver drives the antenna in accordance with the control signal of the microprocessor. The satellite broadcast receiver enables a user to detect satellites fast and see satellite broadcast conveniently.

Abstract: Provided are methods of selectively forming an epitaxial semiconductor layer using an ultra high vacuum chemical vapor deposition (UHVCVD) technique. One embodiment is directed to a method that includes loading a substrate having an insulating layer pattern into a reaction furnace. The reaction furnace is evacuated, and the substrate in the reaction furnace is heated to a temperature of about 550 to about 700° C. A semiconductor source gas is injected into the reaction furnace for a first duration to selectively form an epitaxial semiconductor layer on a region of the heated substrate. The semiconductor source gas remaining in the reaction furnace is then purged for a second duration. A selective etching gas is injected into the reaction furnace for a third duration to selectively remove semiconductor atoms adsorbed on surfaces of the insulating layer pattern. The selective etching gas remaining in the reaction furnace is then purged for a fourth duration.

Abstract: An interface apparatus between a first circuit device and a second circuit device having a first serial communication speed with an external device includes a first buffer unit to store therein data transmitted from the second circuit device; a second buffer unit to store therein data transmitted from the first circuit device; a parallel communication unit to conduct parallel communication between the second circuit device, and the first buffer unit and the second buffer unit; and a serial communication unit to conduct serial communication between the first circuit device, and the first buffer unit and the second buffer unit at a second serial communication speed faster than the first serial communication speed. With this configuration, data transmission speed between circuit devices may be enhanced.

Abstract: A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and is formed on the substrate and extends in a direction away from a major surface of the substrate. The first hard mask layer pattern is formed on a distal surface of the active fin from the substrate. The gate insulation layer is formed on a sidewall portion of the active fin. The first conductive layer pattern includes a metal silicide and is formed on surfaces of the substrate and the gate insulation layer pattern, and on a sidewall of the first hard mask pattern. The source/drain regions are formed in the active fin on opposite sides of the first conductive layer pattern.

Abstract: The invention relates to various substituted isoquinoline-1,3,4-trione, the synthetic method thereof and the use for treating neurodegenerative diseases, especially as the medicine for Alzheimer's disease, apoplexy and brain ischemic injuries.