Patents by Inventor Min Gyu KOO
Min Gyu KOO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10559576Abstract: A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.Type: GrantFiled: July 27, 2017Date of Patent: February 11, 2020Assignee: SK hynix Inc.Inventors: Dong Hwan Lee, Min Gyu Koo, Hyun Heo
-
Patent number: 10176879Abstract: Disclosed are a high voltage switch circuit and a semiconductor memory device including the same. The high voltage switching circuit includes: a control signal generating circuit configured to supply a supply voltage to an internal node and generate a control signal in response to a first enable signal; a well bias generating circuit configured to apply a well bias to a well of a transistor included in the control signal generating circuit in response to a second enable signal; and a switching circuit configured to switch an input voltage to an output voltage in response to the control signal.Type: GrantFiled: March 8, 2017Date of Patent: January 8, 2019Assignee: SK Hynix Inc.Inventors: Dong Hwan Lee, Min Gyu Koo
-
Publication number: 20180075915Abstract: Disclosed are a high voltage switch circuit and a semiconductor memory device including the same. The high voltage switching circuit includes: a control signal generating circuit configured to supply a supply voltage to an internal node and generate a control signal in response to a first enable signal; a well bias generating circuit configured to apply a well bias to a well of a transistor included in the control signal generating circuit in response to a second enable signal; and a switching circuit configured to switch an input voltage to an output voltage in response to the control signal.Type: ApplicationFiled: March 8, 2017Publication date: March 15, 2018Inventors: Dong Hwan LEE, Min Gyu KOO
-
Publication number: 20170323897Abstract: A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.Type: ApplicationFiled: July 27, 2017Publication date: November 9, 2017Inventors: Dong Hwan LEE, Min Gyu KOO, Hyun HEO
-
Patent number: 9754950Abstract: A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.Type: GrantFiled: September 24, 2015Date of Patent: September 5, 2017Assignee: SK Hynix Inc.Inventors: Dong Hwan Lee, Min Gyu Koo, Hyun Heo
-
Publication number: 20160322370Abstract: A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.Type: ApplicationFiled: September 24, 2015Publication date: November 3, 2016Inventors: Dong Hwan LEE, Min Gyu KOO, Hyun HEO
-
Patent number: 9467050Abstract: A semiconductor apparatus includes a voltage supply circuit suitable for outputting a high voltage, a transfer circuit coupled between the voltage supply circuit and a peripheral circuit and suitable for transferring the high voltage to the peripheral circuit and a transfer control circuit suitable for outputting a transfer control signal to the transfer circuit to control the transfer of the high voltage to the peripheral circuit, wherein the transfer control circuit outputs the transfer control signal having a first positive voltage level to a gate of a transistor included in the transfer circuit when the voltage supply circuit outputs the high voltage to the transfer circuit.Type: GrantFiled: September 4, 2014Date of Patent: October 11, 2016Assignee: SK Hynix Inc.Inventors: Yeonghun Lee, Hyun Heo, Min Gyu Koo, Dong Hwan Lee
-
Patent number: 9331089Abstract: The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer.Type: GrantFiled: November 14, 2014Date of Patent: May 3, 2016Assignee: SK Hynix Inc.Inventor: Min Gyu Koo
-
Patent number: 9299447Abstract: A semiconductor device includes a plurality of memory blocks, wherein each of the plurality of memory blocks includes a first select transistor electrically coupled to a common source line, a second select transistor electrically coupled to a bit line, and a plurality of memory cells electrically coupled between the first and second select transistors, and an operation circuit suitable for applying operation voltages for a program operation, a read operation, and an erase operation to a selected memory block selected from the plurality of memory blocks, and applying a first positive voltage to gates of the first select transistors in unselected memory blocks of the plurality of memory blocks when an erase voltage is applied to the common source line during the erase operation.Type: GrantFiled: September 18, 2014Date of Patent: March 29, 2016Assignee: SK Hynix Inc.Inventors: Yeonghun Lee, Hyun Heo, Min Gyu Koo, Dong Hwan Lee
-
Publication number: 20150348634Abstract: A semiconductor memory device includes a plurality of memory cells coupled between a source line and a bit line, a voltage generation circuit suitable for applying an erase voltage to the source line during an erase operation, and a read and to circuit coupled to the bit line through a selection transistor and suitable for applying an operating voltage to a first node of the selection transistor during the erase operation.Type: ApplicationFiled: September 15, 2014Publication date: December 3, 2015Inventors: Min Gyu KOO, Hyun HEO, Dong Hwan LEE
-
Publication number: 20150288283Abstract: A semiconductor apparatus includes a voltage supply circuit suitable for outputting a high voltage, a transfer circuit coupled between the voltage supply circuit and a peripheral circuit and suitable for transferring the high voltage to the peripheral circuit and a transfer control circuit suitable for outputting a transfer control signal to the transfer circuit to control the transfer of the high voltage to the peripheral circuit, wherein the transfer control circuit outputs the transfer control signal having a first positive voltage level to a gate of a transistor included in the transfer circuit when the voltage supply circuit outputs the high voltage to the transfer circuit.Type: ApplicationFiled: September 4, 2014Publication date: October 8, 2015Inventors: Yeonghun LEE, Hyun HEO, Min Gyu KOO, Dong Hwan LEE
-
Publication number: 20150279471Abstract: A semiconductor device includes a plurality of memory blocks, wherein each of the plurality of memory blocks includes a first select transistor electrically coupled to a common source line, a second select transistor electrically coupled to a bit line, and a plurality of memory cells electrically coupled between the first and second select transistors, and an operation circuit suitable for applying operation voltages for a program operation, a read operation, and an erase operation to a selected memory block selected from the plurality of memory blocks, and applying a first positive voltage to gates of the first select transistors in unselected memory blocks of the plurality of memory blocks when an erase voltage is applied to the common source line during the erase operation.Type: ApplicationFiled: September 18, 2014Publication date: October 1, 2015Inventors: Yeonghun LEE, Hyun HEO, Min Gyu KOO, Dong Hwan LEE
-
Patent number: 9018707Abstract: A semiconductor device includes a first transistor group including first transistors, wherein each of the first transistors includes a first gate, and a first source and a first drain disposed symmetrically at both sides of the first gate and having a bent form; and a second transistor group including second transistors, wherein each of the second transistors includes a second gate, and a second source and a second drain disposed symmetrically at both sides of the second gate and having a bent form, wherein the first source and the first drain are bent in a direction opposite to a direction in which the second source and the second drain are bent.Type: GrantFiled: August 31, 2012Date of Patent: April 28, 2015Assignee: SK Hynix Inc.Inventor: Min Gyu Koo
-
Publication number: 20150064894Abstract: The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer.Type: ApplicationFiled: November 14, 2014Publication date: March 5, 2015Inventor: Min Gyu KOO
-
Patent number: 8956950Abstract: A method of manufacturing semiconductor devices includes forming a plurality of patterns spaced apart from each other on a semiconductor substrate, forming a filling layer, not removed in a subsequent process of forming a mask pattern and where the filling layer formed to have a lower height than the plurality of patterns, between the plurality of patterns, forming a mask layer on the entire structure where the filling layer is formed, and forming the mask pattern by removing some of the mask layer so that some of the plurality of patterns is removed.Type: GrantFiled: March 9, 2012Date of Patent: February 17, 2015Assignee: SK Hynix Inc.Inventor: Min Gyu Koo
-
Patent number: 8912575Abstract: The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer.Type: GrantFiled: December 18, 2012Date of Patent: December 16, 2014Assignee: SK Hynix Inc.Inventor: Min Gyu Koo
-
Publication number: 20140054668Abstract: The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer.Type: ApplicationFiled: December 18, 2012Publication date: February 27, 2014Applicant: SK HYNIX INC.Inventor: Min Gyu KOO
-
Patent number: 8520445Abstract: A memory device includes a block switch for transferring operating voltages, supplied to global lines, to local lines coupled to a memory cell array in response to the voltage level of a block selection signal and a negative voltage transfer circuit for transferring a negative voltage as the block selection signal in order to couple the global lines and the local lines when the operating voltage has a negative level and to disconnect the global lines and the local lines from each other when the block selection signal is disabled.Type: GrantFiled: August 31, 2011Date of Patent: August 27, 2013Assignee: SK Hynix Inc.Inventor: Min Gyu Koo
-
Publication number: 20130161752Abstract: A semiconductor device includes a first transistor group including first transistors, wherein each of the first transistors includes a first gate, and a first source and a first drain disposed symmetrically at both sides of the first gate and having a bent form; and a second transistor group including second transistors, wherein each of the second transistors includes a second gate, and a second source and a second drain disposed symmetrically at both sides of the second gate and having a bent form, wherein the first source and the first drain are bent in a direction opposite to a direction in which the second source and the second drain are bent.Type: ApplicationFiled: August 31, 2012Publication date: June 27, 2013Applicant: SK HYNIX INC.Inventor: Min Gyu KOO
-
Publication number: 20120231599Abstract: A method of manufacturing semiconductor devices includes forming a plurality of patterns spaced apart from each other on a semiconductor substrate, forming a filling layer, not removed in a subsequent process of forming a mask pattern and where the filling layer formed to have a lower height than the plurality of patterns, between the plurality of patterns, forming a mask layer on the entire structure where the filling layer is formed, and forming the mask pattern by removing some of the mask layer so that some of the plurality of patterns is removed.Type: ApplicationFiled: March 9, 2012Publication date: September 13, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Min Gyu KOO