Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region.

Abstract: Provided is a tabletop interface system. A tabletop input device diffuses an infrared light emitted based on at least one touch input from a user. A tabletop output device allows the diffused infrared light to pass therethrough to display content information corresponding to at least one touch point. The tabletop recognition device recognizes the at least one touch point by generating a touch image data based on the infrared light passing through the tabletop output device and generates touch point information by using the touch image data. The content server transmits the content information, which corresponds to the touch point information received from the tabletop recognition device, to at least one content client application.

Abstract: The present invention discloses a mask ROM which has excellent compatibility with a logic process and improves integration of a memory cell, and a fabrication method thereof. The mask ROM includes: a substrate where a memory cell array region and a segment select region are defined; first and second trenches respectively formed at the outer portion of the memory cell array region and at the outer portion of a buried layer formation region of the segment select region; an element isolating film and an isolating pattern respectively filling up the first and second trenches; a plurality of buried layers aligned on the substrate in a first direction by a predetermined interval, and surrounded by the isolating pattern; and a plurality of gates aligned in a second direction to cross the buried layers in an orthogonal direction.

Abstract: The present invention discloses a mask ROM which has excellent compatibility with a logic process and improves integration of a memory cell, and a fabrication method thereof. The mask ROM includes: a substrate where a memory cell array region and a segment select region are defined; first and second trenches respectively formed at the outer portion of the memory cell array region and at the outer portion of a buried layer formation region of the segment select region; an element isolating film and an isolating pattern respectively filling up the first and second trenches; a plurality of buried layers aligned on the substrate in a first direction by a predetermined interval, and surrounded by the isolating pattern; and a plurality of gates aligned in a second direction to cross the buried layers in an orthogonal direction.

Abstract: The present invention discloses a mask ROM which has excellent compatibility with a logic process and improves integration of a memory cell, and a fabrication method thereof. The mask ROM includes: a substrate where a memory cell array region and a segment select region are defined; first and second trenches respectively formed at the outer portion of the memory cell array region and at the outer portion of a buried layer formation region of the segment select region; an element isolating film and an isolating pattern respectively filling up the first and second trenches; a plurality of buried layers aligned on the substrate in a first direction by a predetermined interval, and surrounded by the isolating pattern; and a plurality of gates aligned in a second direction to cross the buried layers in an orthogonal direction.

Abstract: The present invention discloses a mask ROM which has excellent compatibility with a logic process and improves integration of a memory cell, and a fabrication method thereof. The mask ROM includes: a substrate where a memory cell array region and a segment select region are defined; first and second trenches respectively formed at the outer portion of the memory cell array region and at the outer portion of a buried layer formation region of the segment select region; an element isolating film and an isolating pattern respectively filling up the first and second trenches; a plurality of buried layers aligned on the substrate in a first direction by a predetermined interval, and surrounded by the isolating pattern; and a plurality of gates aligned in a second direction to cross the buried layers in an orthogonal direction.

Abstract: A method that includes: providing a substrate where a memory cell array region and a peripheral region are defined; forming a buried layer on the substrate; forming a gate material by positioning a gate insulating film on the substrate having the buried layer; forming first gates by covering the peripheral region, and etching the gate material of the memory cell array region according to a photolithography process; forming an insulating pattern on the substrate to fill up a space between the first gates and expose the surfaces of the first gates; forming second gates by covering the memory cell array region, and etching the gate material of the peripheral region according to the photolithography process; and forming a low resistance layer on the first gates, and simultaneously forming a source/drain at both sides of the second gates, by doping an impurity to the substrate having the first and second gates.

Abstract: The present invention relates to a flash memory cell and fabricating method therefore, including a semiconductor substrate having first type impurity, a first gate insulating layer on a first certain part of the semiconductor substrate, a buried insulating layer on a second certain part of the semiconductor substrate, the buried insulating layer being connected to the first gate insulating layer, a floating gate on the first gate insulating layer wherein the floating gate extends on and is overlapped with the buried insulating layer in part, a second gate insulating layer on the floating gate, a third gate insulating layer at a lateral surface of the floating gate, a control gate on the second gate insulating layer wherein one side of the control gate corresponds to that of the floating gate and the other side of the control gate does not correspond to that of the control gate and the one side of said control gate overlaps over the buried insulating layer, a fourth gate-insulating layer on the control gate, a

Abstract: In the flash memory cell, a floating gate overlaps a thick insulator covering a source region and overlaps a thin insulator covering a channel region. A control gate formed over the floating gate also partially overlaps the thick insulator. A thin sidewall spacer is formed on the floating gate sidewall, and a thick sidewall space is formed on the control gate sidewall. An erase gate is formed adjacent to the thin and thick sidewall spacers.

Abstract: The present invention relates to flash memory cell and fabricating method therefor, including a semiconductor substrate having first typed impurity, a first gate insulating layer on a first certain part of the semiconductor substrate, a buried insulating layer on a second certain part of the semiconductor substrate, the buried insulating layer being connected to the first gate insulating layer, a floating gate on the first gate insulating layer wherein the floating gate extends on and is overlapped with the buried insulating layer in part, a second gate insulating layer on the floating gate, a third gate insulating layer at a lateral surface of the floating gate, a control gate on the second gate insulating layer wherein one side of the control gate corresponds to that of the floating gate and the other side of the control gate does not correspond to that of the control gate and the one side of said control gate overlaps over the buried insulating layer, a fourth gate insulating layer on the control gate, an

Abstract: Semiconductor memory and a method for fabricating the same, in which sides of a floating gate is formed to have a streamlined profile, for improving a device performance, the semiconductor memory including a semiconductor substrate, a plurality of field oxide films formed at fixed intervals in one direction for isolating an active region between adjacent field oxide films, a plurality of control gates formed at fixed intervals in a second direction perpendicular to the field oxide films, a plurality of floating gates respectively formed under the control gates spaced a distance from each other each having edge portions in the second direction with moderate slopes, an interlayer insulating layer formed at interfaces between the floating gate and the control gate, and source/drain formed in surfaces of a semiconductor substrate on both sides of the control gate.

Abstract: Semiconductor memory and a method for fabricating the same, in which sides of a floating gate is formed to have a streamlined profile, for improving a device performance, the semiconductor memory including a semiconductor substrate, a plurality of field oxide films formed at fixed intervals in one direction for isolating an active region between adjacent field oxide films, a plurality of control gates formed at fixed intervals in a second direction perpendicular to the field oxide films, a plurality of floating gates respectively formed under the control gates spaced a distance from each other each having edge portions in the second direction with moderate slopes, an interlayer insulating layer formed at interfaces between the floating gate and the control gate, and source/drain formed in surfaces of a semiconductor substrate on both sides of the control gate.

Abstract: Semiconductor memory device and method is provided for a stacked gate type flash semiconductor memory device. The semiconductor memory device improves programming and erasing operation efficiency. A gate oxide layer and a floating gate are formed to be stacked on a substrate. A first dielectric layer and a control gate are formed to be stacked on the floating gate. A second dielectric layer is formed on both sides of the floating gate and first and second semiconductor sidewalls are formed on the second dielectric layer on the both sides of the floating gate. Impurity regions are formed in the substrate at the both sides of the floating gate and a wire layer is formed to contact with the semiconductor sidewalls and each of the impurity regions.

Abstract: A flash memory is disclosed including a second conductivity-type substrate having first conductivity-type first and second impurity regions spaced apart from each other by a predetermined distance; a second conductivity-type floating gate formed above part of the first impurity region; a first conductivity-type floating gate formed over the second conductivity-type floating gate; and an insulating layer and first conductivity-type control gate sequentially formed on the first conductivity-type floating gate.

Abstract: A non-volatile memory device includes a substrate, a projection having two sides formed on the substrate, a floating gate formed on the projection, a control gate formed on the substrate including the floating gate, a first impurity region formed in the substrate extended from one side of the projection, and a second impurity region formed in the substrate at the other side of the projection and in the substrate extended from the other side of the projection.

Abstract: Semiconductor memory device and method is provided for a stacked gate type flash semiconductor memory device. The semiconductor memory device improves programming and erasing operation efficiency. A gate oxide layer and a floating gate are formed to be stacked on a substrate. A first dielectric layer and a control gate are formed to be stacked on the floating gate. A second dielectric layer is formed on both sides of the floating gate and first and second semiconductor sidewalls are formed on the second dielectric layer on the both sides of the floating gate. Impurity regions are formed in the substrate at the both sides of the floating gate and a wire layer is formed to contact with the semiconductor sidewalls and each of the impurity regions.

Abstract: A nonvolatile memory device includes: a substrate having field and active regions; a field insulating layer formed on the field region; a first gate insulating layer formed on the active region; a floating gate formed on the first gate insulating layer and on a portion of the field insulating layer, the portion extending from the first gate insulating layer, the floating gate being separated from the field insulating layer; a second gate insulating layer formed on the surface of the floating gate; a control gate formed on the second gate insulating layer; and an impurity region formed in a portion of the substrate, the portion being placed on both sides of the control gate.