Abstract: A semiconductor device includes a connector layer; a dielectric layer over the connector layer; and a conductive element in the dielectric layer, the conductive element including: a first region having a first uniform width; a second region having a second uniform width, wherein the second uniform width is less than the first uniform width; and a shoulder between the first region and the second region, wherein an angle of the shoulder relative to a top surface of the connector layer is greater than 20 degrees and less than 70 degrees.

Abstract: A method includes depositing a metallic hardmask over a dielectric layer. The method further includes etching a metallic hardmask opening in the metallic hardmask to expose a top surface of the dielectric layer. Th method further includes modifying a sidewall of the metallic hardmask opening by adding non-metal atoms into the metallic hardmask. The method further includes depositing a conductive material in the metallic hardmask opening.

Abstract: The semiconductor device includes a semiconductor fin, and a gate stack over the semiconductor fin. The gate stack includes a gate dielectric layer over a channel region of the semiconductor fin, a work function material layer over the gate dielectric layer, wherein the work function material layer includes dopants, and a gate electrode layer over the work function material layer. The gate dielectric layer is free of the dopants.

Abstract: A method of fabricating a semiconductor device includes forming a dummy gate structure over a semiconductor fin. The dummy gate structure includes a dummy gate stack and gate spacers along sidewalls of the dummy gate stack. The method further includes forming an inter-layer dielectric (ILD) layer surrounding the dummy gate structure, removing the dummy gate stack to provide an opening exposing a channel region of the semiconductor fin, depositing a gate dielectric layer over bottom and sidewalls of the opening and over the ILD layer, forming a doped work function material layer over the gate dielectric layer using an in-situ doping process, and depositing a gate electrode layer over the doped work function material layer.

Abstract: A method includes depositing a metallic hardmask over a dielectric layer. The method further includes etching a metallic hardmask opening in the metallic hardmask to expose a top surface of the dielectric layer. The method further includes modifying a sidewall of the metallic hardmask opening by adding non-metal atoms into the metallic hardmask. The method further includes depositing a conductive material in the metallic hardmask opening.

Abstract: A method of making a dual damascene interconnect includes operations of depositing a metal hardmask over a dielectric layer; etching a metal hardmask opening in the metal hardmask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer, to expose a top surface of a base conductive layer; modifying a sidewall of the metal hardmask opening; and depositing a conductive material in the metal hardmask opening and the at least one interconnect opening.

Abstract: The semiconductor device includes a semiconductor fin, and a gate stack over the semiconductor fin. The gate stack includes a gate dielectric layer over a channel region of the semiconductor fin, a work function material layer over the gate dielectric layer, wherein the work function material layer includes dopants, and a gate electrode layer over the work function material layer. The gate dielectric layer is free of the dopants.

Abstract: A method of making a dual damascene interconnect includes operations of depositing a metal hardmask over a dielectric layer; etching a metal hardmask opening in the metal hardmask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer, to expose a top surface of a base conductive layer; modifying a sidewall of the metal hardmask opening; and depositing a conductive material in the metal hardmask opening and the at least one interconnect opening.