Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A splicing device includes a first splicing unit and a second splicing unit. The first splicing unit includes a first substrate, a first light-emitting unit, and a second light-emitting unit. The second splicing unit includes a second substrate, a third light-emitting unit, and a fourth light-emitting unit. P is a pitch between the first light-emitting unit and the second light-emitting unit, and a pitch between the third light-emitting unit and the fourth light-emitting unit. LA1 is a horizontal distance from a center of the second light-emitting unit to a first reference plane. LB3 is a horizontal distance from a boundary between a light-emitting surface of the second splicing unit and a second reference plane to the first reference plane. LB1x and LB1y are respectively a horizontal component and a vertical component of a distance from the boundary to a center of the third light-emitting unit.

Abstract: An electronic device is provided. The electronic device includes: a support structure, a heat-dissipation layer, a first adhesive and an electronic panel. The heat-dissipation layer is disposed on the support structure and includes at least one first hole. The first adhesive is disposed in the at least one first hole. The electronic panel is disposed on the heat-dissipation layer.

Abstract: A detection circuit and a detection method are provided. The detection circuit is suitable for a system-on-chip (SoC). The SoC is coupled to an alarm pin of a DDR4 memory through a connection pad, and the detection circuit includes a control circuit coupled to the connection pad. In response to the DDR4 memory performing a refresh process or a specific event occurring, the control circuit outputs a test signal with a first voltage level to the connection pad, and determines whether a voltage level of the connection pad is tied to a second voltage level. In response to determining that the voltage level of the connection pad is tied to the second voltage level, the control circuit outputs an interrupt signal to a CPU of the SoC, and the interrupt signal indicates that the alarm pin of the DDR4 memory is not controlled normally by the DDR4 memory.

Abstract: The present disclosure discloses a memory access interface device. The clock generation circuit thereof generates reference clocks. Each of the DDR access signal transmission circuits thereof, under a DDR mode, adjusts a phase and a duty cycle of one of DDR access signals according to one of DDR reference clock signals to generate one of output access signals to access the memory device. The data signal transmission circuit thereof, under an SDR mode, applies a minimum latency on an SDR data signal according to the command and address reference clock signal to generate an output SDR data signal to access the memory device. The command and address signal transmission circuit thereof, under either the DDR or SDR mode, applies a programmable latency on a command and address signal according to the command and address reference clock signal to generate an output command and address signal to access the memory device.

Abstract: A memory controller comprising: a delay circuit, configured to use a first delay value and a second delay value to respectively delay a sampling clock signal to generate a first and a second delayed sampling clock signal; a sampling circuit, configured to use a first edge of the first delayed sampling clock signal to sample a data signal to generate a first sampling value, and configured to use a second edge of the second delayed sampling clock signal to sample the data signal to generate a second sampling value; and a calibrating circuit, configured to generate a sampling delay value according to the first delay value based on the first sampling value and the second sampling value. The delay circuit uses the sampling delay value to generate an adjusted sampling clock signal and the sampling circuit sample the data signal by the adjusted sampling clock signal.

Abstract: An electronic device is provided. The electronic device includes: a support structure, a heat-dissipation layer, a first adhesive and an electronic panel. The heat-dissipation layer is disposed on the support structure and includes at least one first hole. The first adhesive is disposed in the at least one first hole. The electronic panel is disposed on the heat-dissipation layer.

Abstract: A method of fabricating a pixel structure for an organic light-emitting display (OLED) is disclosed. A substrate having at least a sub-pixel region is provided. An auxiliary electrode layer and an insulating layer are formed on the substrate in the sub-pixel region, wherein the insulating layer has an opening to expose the auxiliary electrode layer. A lower electrode layer, an organic light emission layer, and an upper electrode layer are formed on the substrate, wherein the organic light emission layer fills the opening in the insulating layer. Another opening is formed in the upper electrode layer and the organic light emission layer directly on the opening in the insulating layer by performing a laser process, such that the upper electrode layer and the auxiliary electrode layer are welded together through the opening in the upper electrode layer and the organic light emission layer.

Abstract: An organic light emitting display device includes a first substrate, an organic light emitting diode array, a thin film encapsulation layer, a second substrate, a sealant member and a buffer layer. First substrate has a light emitting region and a non-light emitting region. OLED array is configured in light emitting region covered by encapsulation layer. Second substrate has a color filter array and is arranged opposite first substrate. Sealant member is disposed between first and second substrates. Buffer layer has a first light shielding layer disposed thereon, is arranged between first and second substrates, and is configured in light emitting region. Light shielding layer is arranged between buffer layer and encapsulation layer. The sum of the buffer layer's thickness and a gap distance from buffer layer to encapsulation layer has a range from 5 to 20 ?m. Buffer layer has hardness smaller than that of the color filter array.

Abstract: An organic light emitting display device includes a first substrate, an organic light emitting diode array, a thin film encapsulation layer, a second substrate, a sealant member and a buffer layer. First substrate has a light emitting region and a non-light emitting region. OLED array is configured in light emitting region covered by encapsulation layer. Second substrate has a color filter array and is arranged opposite first substrate. Sealant member is disposed between first and second substrates. Buffer layer has a first light shielding layer disposed thereon, is arranged between first and second substrates, and is configured in light emitting region. Light shielding layer is arranged between buffer layer and encapsulation layer. The sum of the buffer layer's thickness and a gap distance from buffer layer to encapsulation layer has a range from 5 to 20 ?m. Buffer layer has hardness smaller than that of the color filter array.

Abstract: A method of fabricating a pixel structure for an organic light-emitting display (OLED) is disclosed. A substrate having at least a sub-pixel region is provided. An auxiliary electrode layer and an insulating layer are formed on the substrate in the sub-pixel region, wherein the insulating layer has an opening to expose the auxiliary electrode layer. A lower electrode layer, an organic light emission layer, and an upper electrode layer are formed on the substrate, wherein the organic light emission layer fills the opening in the insulating layer. Another opening is formed in the upper electrode layer and the organic light emission layer directly on the opening in the insulating layer by performing a laser process, such that the upper electrode layer and the auxiliary electrode layer are welded together through the opening in the upper electrode layer and the organic light emission layer.