Abstract: The present disclosure relates to a simulation apparatus for secondary battery production.

Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.

Abstract: Disclosed is a memory device including a row decoder generating word line (WL) control signals based on a row address from an external device, a first sub-array including memory cells connected to word lines, a first sub-word line driver (SWD) providing a selection voltage or a non-selection voltage to odd-numbered word lines of the word lines based on odd-numbered WL control signals corresponding to the odd-numbered word lines, and a second SWD providing the selection voltage or the non-selection voltage to even-numbered word lines of the word lines based on even-numbered WL control signals corresponding to the even-numbered word lines. The first SWD applies the non-selection voltage to non-selection word lines of the even-numbered word lines, in response to the even-numbered WL control signals, and the second SWD applies the non-selection voltage to non-selection word lines of the odd-numbered word lines, in response to the odd-numbered WL control signals.

Abstract: A 3D semiconductor memory device includes a first through-structure on a substrate, the first through-structure comprising first and second conductive pillars spaced apart from each other in a first direction, an electrode adjacent to the first through-structure, the electrode horizontally extending in the first direction, and a ferroelectric layer and a channel layer between the electrode and the first and second conductive pillars. The channel layer connects the first and second conductive pillars to each other. The ferroelectric layer is disposed between the electrode and the channel layer. The ferroelectric layer extends from a sidewall of the first conductive pillar to a sidewall of the second conductive pillar along the channel layer when viewed in a plan view.

Abstract: The substrate processing apparatus of the present invention comprises a hot plate for heating a substrate; and a cooling unit for cooling the hot plate; wherein the cooling unit includes a support plate having a space formed between the support plate and the hot plate, and a plurality of nozzles installed on the support plate and for supplying cooling gas to a bottom surface of the hot plate, wherein an outdoor air inlet passage provided in a through structure is provide in the support plate, wherein a portion of the outdoor air inlet passage forms a first region, through which a cable passes, and the remaining portion forms a second region, through which the cable does not pass and outdoor air introduces.

Abstract: The inventive concept provides a substrate treating method. The substrate treating method includes supplying a dissolving solution onto a rotating substrate; and supplying, after the supplying a dissolution solution, a treating liquid including a polymer onto the rotating substrate to form a liquid film.

Abstract: A semiconductor device includes a first single crystal semiconductor pattern including a first source/drain region, a second source/drain region, and a first vertical channel region between the first source/drain region and the second source/drain region, the second source/drain region being at a higher level than the first source/drain region; a first gate electrode facing a first side surface of the first single crystal semiconductor pattern; a first gate dielectric layer, the first gate dielectric layer including a portion between the first single crystal semiconductor pattern and the first gate electrode; and a complementary structure in contact with a second side surface of the first single crystal semiconductor pattern, wherein the complementary structure includes an oxide semiconductor layer.

Abstract: The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes discharging a treating liquid including a polymer and a solvent onto a substrate; and solidifying a liquid film of the treating liquid by volatilizing the solvent from the treating liquid on the substrate, and wherein the solidifying a liquid film comprises a first period of stopping the rotation of the substrate or rotating the substrate at a first speed for a first time period.

Abstract: A semiconductor device may include a bit line extending in a first direction, a semiconductor pattern on the bit line, the semiconductor pattern including first and second vertical portions, which are opposite to each other in the first direction, and a horizontal portion connecting the first and second vertical portions, first and second word lines on the horizontal portion to be adjacent to the first and second vertical portions, respectively, and a gate insulating pattern between the first vertical portion and the first word line and between the second vertical portion and the second word line. A bottom surface of the horizontal portion may be located at a height that is lower than or equal to the uppermost surface of the bit line.

Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a peripheral circuit structure including peripheral circuits on a semiconductor substrate and a first dielectric layer on the peripheral circuits, a cell array structure on the semiconductor substrate, and a shield layer between the peripheral circuit structure and the cell array structure. The cell array structure includes bit lines, first and second active patterns on the bit lines, first word lines that extend in a second direction on the first active patterns, second word lines that extend in the second direction on the second active patterns, data storage patterns on the first and second active patterns, and a second dielectric layer on the semiconductor substrate. A hydrogen concentration of the first dielectric layer is greater than that of the second dielectric layer.

Abstract: A semiconductor device includes a first conductive line that extends in a first horizontal direction, a plurality of semiconductor patterns on the first conductive line and spaced apart from each other in the first horizontal direction wherein each of the semiconductor patterns includes a first vertical part and a second vertical part that are opposite to each other in the first horizontal direction, a second conductive line that extends in a second horizontal direction between the first vertical part and the second vertical part of each of the semiconductor patterns, the second horizontal direction intersecting the first horizontal direction, a gate dielectric pattern between the first vertical part and the second vertical part and between the second vertical part and the second conductive line, and a blocking pattern between neighboring semiconductor patterns.

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, a source electrode in contact with a first sidewall of the channel layer, and a drain electrode in contact with a second sidewall of the channel layer. The second sidewall is opposite to the first sidewall. The channel layer includes a first channel pattern in contact with one of the source electrode and the drain electrode, and a second channel pattern between the first channel pattern and the gate electrode. The first channel pattern and the second channel pattern includes oxide semiconductor materials different from each other. A portion of the source electrode and a portion of the drain electrode overlap a portion of the gate electrode.

Abstract: There are provided a substrate treating apparatus and a substrate treating method. The substrate treating apparatus includes: a stage on which a substrate is seated, in a chamber; and a treatment liquid supply apparatus supplying a treatment liquid containing a solvent and a solute onto the substrate, wherein the treatment liquid supply apparatus supplies the treatment liquid onto the substrate while moving from a center of the substrate to an outer peripheral surface of the substrate.

Abstract: A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

Abstract: An exemplary embodiment of the present invention provides a substrate treating method including removing particles formed on a substrate by continuously performing a process of supplying a treatment liquid including a polymer and a solvent onto the substrate, forming a solidified liquid film by volatilizing the solvent in the treatment liquid, removing the solidified liquid film from the substrate by supplying a stripping liquid onto the substrate; and supplying a rinse liquid onto the substrate.

Abstract: The present invention relates to a bonding apparatus for a power terminal of a heating plate, for bonding the power terminal supplying power to a heating wire of a substrate. The bonding apparatus for a power terminal of a heating plate comprises: a chamber; a stage which is disposed in an inner space of the chamber and on which the substrate is placed; an upper press portion disposed in the inner space of the chamber to face the stage, provided to be vertically movable, and having a terminal fixing portion configured to fix the power terminal; and an elevating driver configured to move the upper press portion up and down, wherein the terminal fixing portion further includes a magnetic holder configured to hold the power terminal by a magnetic force.

Abstract: A semiconductor memory device includes bit lines disposed on a substrate and extending in a first direction in parallel to each other, a hydrogen supply insulating layer including hydrogen and filling a space between the bit lines, a source pattern located on each of the bit lines and being in partial contact with the hydrogen supply insulating layer, a hydrogen diffusion barrier layer covering a top surface of the hydrogen supply insulating layer and being in contact with a side surface of the source pattern, a first channel pattern located on the source pattern, a first word line being adjacent to a side surface of the first channel pattern and crossing over the bit lines, and a landing pad on the first channel pattern.

Abstract: Provided are a substrate treatment apparatus and method for treating a substrate by simultaneously providing a stripper for peeling a coating film on the substrate to an entire surface of the substrate. The substrate treatment method includes discharging a first liquid onto a substrate by using a first nozzle, and forming a coating film collecting particles by using the first liquid; spraying a second liquid on the substrate by using a second nozzle, and peeling the coating film from the substrate by using the second liquid; and discharging a third liquid onto the substrate by using a third nozzle, and rinsing the coating film from the substrate by using the third liquid, wherein in the peeling of the coating film, the second liquid is simultaneously sprayed on an entire surface of the substrate.

Abstract: A heating device capable of heating a processing liquid stably and efficiently is provided.