Patents by Inventor Min-hee UH

Min-hee UH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11569206
    Abstract: An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: January 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-hee Uh, Sung-min Kang, Jun-gu Kang, Seung-hee Go, Young-mok Kim
  • Patent number: 11302680
    Abstract: A display driver integrated circuit (IC) device includes a first substrate having a first front surface and a first back surface; a first interlayer insulating layer on the first front surface; a wiring layer in the first interlayer insulating layer; a first bonding insulating layer on the first interlayer insulating layer; a second substrate having a second front surface and a second back surface, the second front surface being disposed toward the first front surface; a second interlayer insulating layer on the second front surface a second bonding insulating layer on the second interlayer insulating layer and physically bonded to the first bonding insulating layer; and a back via stack structure penetrating the second substrate, the second interlayer insulating layer, the second bonding insulating layer, the first bonding insulating layer, and the first interlayer insulating layer and electrically connected to the wiring layer.
    Type: Grant
    Filed: May 16, 2021
    Date of Patent: April 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-hee Go, Min-Hee Uh
  • Patent number: 11183429
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate including a first region and a second region, forming a first channel layer in the first region of the substrate, forming an isolation region in the substrate to electrically isolate a portion of the first region from a portion of the second region, etching an upper surface of the second region of the substrate, forming a protection layer covering the first channel layer in the first region of the substrate and the second region of the substrate, removing the protection layer on the second region of the substrate, forming a gate insulation material layer on the protection layer and on the second region of the substrate, and removing the gate insulation material layer and the protection layer on the first region of the substrate.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: November 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Min Kang, Kyung Min Kim, Young Mok Kim, Min Hee Uh
  • Publication number: 20210296287
    Abstract: An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Inventors: Min-hee UH, Sung-min KANG, Jun-gu KANG, Seung-hee GO, Young-mok KIM
  • Publication number: 20210272940
    Abstract: A display driver integrated circuit (IC) device includes a first substrate having a first front surface and a first back surface; a first interlayer insulating layer on the first front surface; a wiring layer in the first interlayer insulating layer; a first bonding insulating layer on the first interlayer insulating layer; a second substrate having a second front surface and a second back surface, the second front surface being disposed toward the first front surface; a second interlayer insulating layer on the second front surface a second bonding insulating layer on the second interlayer insulating layer and physically bonded to the first bonding insulating layer; and a back via stack structure penetrating the second substrate, the second interlayer insulating layer, the second bonding insulating layer, the first bonding insulating layer, and the first interlayer insulating layer and electrically connected to the wiring layer.
    Type: Application
    Filed: May 16, 2021
    Publication date: September 2, 2021
    Inventors: Seung-hee GO, Min-hee UH
  • Patent number: 11049846
    Abstract: An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: June 29, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-hee Uh, Sung-min Kang, Jun-gu Kang, Seung-hee Go, Young-mok Kim
  • Patent number: 11024615
    Abstract: A display driver integrated circuit (IC) device includes a first substrate having a first front surface and a first back surface; a first interlayer insulating layer on the first front surface; a wiring layer in the first interlayer insulating layer; a first bonding insulating layer on the first interlayer insulating layer; a second substrate having a second front surface and a second back surface, the second front surface being disposed toward the first front surface; a second interlayer insulating layer on the second front surface a second bonding insulating layer on the second interlayer insulating layer and physically bonded to the first bonding insulating layer; and a back via stack structure penetrating the second substrate, the second interlayer insulating layer, the second bonding insulating layer, the first bonding insulating layer, and the first interlayer insulating layer and electrically connected to the wiring layer.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: June 1, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-hee Go, Min-hee Uh
  • Publication number: 20200312727
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate including a first region and a second region, forming a first channel layer in the first region of the substrate, forming an isolation region in the substrate to electrically isolate a portion of the first region from a portion of the second region, etching an upper surface of the second region of the substrate, forming a protection layer covering the first channel layer in the first region of the substrate and the second region of the substrate, removing the protection layer on the second region of the substrate, forming a gate insulation material layer on the protection layer and on the second region of the substrate, and removing the gate insulation material layer and the protection layer on the first region of the substrate.
    Type: Application
    Filed: December 10, 2019
    Publication date: October 1, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung Min KANG, Kyung Min KIM, Young Mok KIM, Min Hee UH
  • Publication number: 20200294978
    Abstract: A display driver integrated circuit (IC) device includes a first substrate having a first front surface and a first back surface; a first interlayer insulating layer on the first front surface; a wiring layer in the first interlayer insulating layer; a first bonding insulating layer on the first interlayer insulating layer; a second substrate having a second front surface and a second back surface, the second front surface being disposed toward the first front surface; a second interlayer insulating layer on the second front surface a second bonding insulating layer on the second interlayer insulating layer and physically bonded to the first bonding insulating layer; and a back via stack structure penetrating the second substrate, the second interlayer insulating layer, the second bonding insulating layer, the first bonding insulating layer, and the first interlayer insulating layer and electrically connected to the wiring layer.
    Type: Application
    Filed: September 10, 2019
    Publication date: September 17, 2020
    Inventors: Seung-hee GO, Min-hee UH
  • Publication number: 20200294970
    Abstract: An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.
    Type: Application
    Filed: August 22, 2019
    Publication date: September 17, 2020
    Inventors: Min-hee UH, Sung-min KANG, Jun-gu KANG, Seung-hee GO, Young-mok KIM