Abstract: A memory system includes a memory device including a first memory region of higher density storage and a second memory region of lower density storage; and a controller configured to control the memory device to sequentially perform a backup program operation to the second memory region and perform coarse program and fine program operations to the first memory region for each of data chunks, wherein the controller controls, for at least two among the data chunks, the memory device to first perform the coarse program and then perform the fine program operation, and wherein the controller controls the memory device to perform the backup program operation without a program verify process.

Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a read operation controller configured to provide a read command to a memory device and receive read data corresponding to the read command, a read fail determiner configured to determine, based on the read data, whether a read operation has passed or failed, and to generate read information including a result of the read operation and information about performance of the read operation and a read fail processor configured to select, based on the read information, one of a read retry operation, among a plurality of read retry operations, to be performed on the selected page and an operation of setting a control time for a bit line coupled to the selected page, and to control the memory device to perform the selected operation.

Abstract: A memory controller controls a memory device including a register for storing a plurality of parameters. The memory controller includes: a register information storage configured to store the plurality of parameters as setting parameters, a register controller configured to provide the memory device with a parameter change command for requesting a selected parameter to be changed to a set value, and acquire, from the memory device, Cyclic Redundancy Check (CRC) calculation information obtained by performing a CRC calculation on the plurality of parameters including the selected parameter, a CRC reference information generator configured to generate CRC reference information by performing a CRC calculation on the setting parameters including a setting parameter changed to the set value, and a CRC information comparator configured to determine whether an error is included in the plurality of parameters according to a comparison result between the CRC calculation information and the CRC reference information.

Abstract: In a memory device having improved reliability, the memory device includes: a memory cell array including memory cells; a program operation controller configured to perform a program operation on the memory cells to any one state among first to nth states; a voltage generator configured to generate operating voltages respectively corresponding to the first to nth states in the program operation; a verify operation controller configured to verify whether the program operation performed on selected memory cells to a kth state, has been completed, and count a number of over-programmed memory cells having a threshold voltage greater than a threshold voltage corresponding to the kth state among the selected memory cells; and an over-program manager configured to increase operating voltages corresponding to (k+1)th to nth states to be greater than default values according to the number of over-programmed memory cells.

Abstract: A memory controller controls a memory device including a plurality of memory blocks and a plurality of power modules respectively providing voltages to a plurality of word line groups, the memory controller comprising: a fail block detector detecting fail blocks on which an erase operation has failed among the plurality of memory blocks, and detecting fail word line groups among a plurality of word line groups included in each of the fail blocks; a fail block manager detecting, among the plurality of power modules, a defective power module providing the voltages to two or more fail word line groups each included in a different fail block among the fail blocks; and a power defect controller controlling the memory device such that the defective power module is changed to another power module among the plurality of power modules.

Abstract: In a memory device having improved reliability, the memory device includes: a memory device comprising: a memory cell array including memory cells; a program operation controller configured to perform a program operation on the memory cells to any one state among first to nth states; a voltage generator configured to generate operating voltages respectively corresponding to the first to nth states in the program operation; a verify operation controller configured to verify whether the program operation performed on selected memory cells to a kth state, has been completed, and count a number of over-programmed memory cells having a threshold voltage greater than a threshold voltage corresponding to the kth state among the selected memory cells; and an over-program manager configured to increase operating voltages corresponding to (k+1)th to nth states to be greater than default values according to the number of over-programmed memory cells.

Abstract: In a memory controller for controlling a memory device including a memory block coupled to a plurality of word lines, the memory block including a plurality of memory cells respectively coupled to the plurality of word lines, the memory controller comprising: an operating time calculator configured to calculate program operating times taken to perform a program operation on the memory cells respectively coupled to the plurality of word lines; and an operating voltage determiner configured to determine an erase voltage to be used to erase a memory block by comparing a first program operating time, among the program operating times calculated by the operating time calculator, with the other program operating times, except the first program operating time, among the program operating times.

Abstract: The present disclosure relates to an electronic device. A storage device includes a memory device configured to include a plurality of memory cells and a memory controller configured to determine a read voltage for a read operation to be performed on the memory device according to whether the read operation is a cache read operation.

Abstract: Provided herein is a memory device and a method of operating the memory device. The memory device may include a one or more memory blocks, one or more peripheral circuits configured to perform an erase operation and a threshold voltage distribution scan operation on a selected memory block, and a control logic configured to control the one or more peripheral circuits, and determine the selected memory block to be a normal memory block or a defective memory block based on a result of the threshold voltage distribution scan operation.

Abstract: Provided herein may be a memory device, a memory system having the memory device, and a method of operating the memory device. The memory device may include a memory cell array configured to store data, a peripheral circuit configured to perform a program operation on the memory cell array, and a control logic configured to perform the program operation by controlling the peripheral circuit and to perform a status check operation after the program operation. Here, the control logic may be configured to, based on a determination that the status check operation has passed, perform a number-of-program pulses comparison operation by comparing a number of program pulses used in the program operation to a first preset range.

Abstract: A semiconductor device includes memory blocks including a plurality of strings in which memory cells are coupled between select transistors; a peripheral circuit suitable for erasing or programming the select transistors and the memory cells, which are included in a selected memory block among the memory blocks; and a control circuit suitable for controlling the peripheral circuit to erase the select transistors and the memory cells, increasing a threshold voltage of the select transistors within a range below an erase level, and increasing the threshold voltage of the select transistors up to a program level.

Abstract: A semiconductor device includes memory blocks including a plurality of strings in which memory cells are coupled between select transistors; a peripheral circuit suitable for erasing or programming the select transistors and the memory cells, which are included in a selected memory block among the memory blocks; and a control circuit suitable for controlling the peripheral circuit to erase the select transistors and the memory cells, increasing a threshold voltage of the select transistors within a range below an erase level, and increasing the threshold voltage of the select transistors up to a program level.

Abstract: A method of operating a semiconductor device includes storing a supplying condition of a read voltage inputted from an external source into an internal register to perform a read operation of memory cells, performing the read operation repetitively with changing levels of the read voltage according to the supplying condition of the read voltage in the event that the number of error bits in a data read from the memory cells exceeds an allowable range, and storing an iteration number of the read operation in the internal register in case the number of the error bits falls within the allowable range.

Abstract: A method of operating a semiconductor device includes storing a supplying condition of a read voltage inputted from an external source into an internal register to perform a read operation of memory cells, performing the read operation repetitively with changing levels of the read voltage according to the supplying condition of the read voltage in the event that the number of error bits in a data read from the memory cells exceeds an allowable range, and storing an iteration number of the read operation in the internal register in case the number of the error bits falls within the allowable range.