Patents by Inventor Min Ho Jo

Min Ho Jo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240119186
    Abstract: Systems and methods for executing a package simulation for secondary battery production by one or mom processor to perform operations. The operations include executing an apparatus operating unit comprising a 3D package apparatus related to secondary battery production, checking quality of a material produced by the 3D package apparatus, executing a facility operating unit comprising a plurality of adjustment parameters for determining an operation of the 3D package apparatus, obtaining at least one of first user action information obtained through the apparatus operating unit or first user condition information obtained through the facility operating unit, determining at least one of a material checking, the operation of the 3D package apparatus, or a self-inspection based on at least one of the first user action information or the first user condition information, and executing the operation of the 3D package apparatus.
    Type: Application
    Filed: July 26, 2022
    Publication date: April 11, 2024
    Inventors: Min Hee KWON, Moon Kyu JO, Daewoon JUNG, Youngduk KIM, Nam Hyuck KIM, Su Ho JEON
  • Publication number: 20240119856
    Abstract: A simulation apparatus and a simulation method of Double Side Folding and End of Line (DSF&EOL) for secondary battery production are provided.
    Type: Application
    Filed: July 26, 2022
    Publication date: April 11, 2024
    Inventors: Min Hee Kwon, Moon Kyu Jo, Daewoon Jung, Youngduk Kim, Nam Hyuck Kim, Su Ho Jeon
  • Patent number: 11939489
    Abstract: Provided is a composition for surface treatment of a steel sheet, the composition having excellent resistance to an acid, such as sulfuric acid, and to a coated steel sheet to which the composition for surface treatment is applied, wherein the composition for surface treatment comprises 30-50% wt % of colloidal silica containing 5-20 nm-sized silica, 40-60% wt % of silane containing three or more alkoxy groups, 5-15 wt % of an acrylate-based organic monomer, 0.01-1 wt % of an acid, and 1-15 wt % of a solvent.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: March 26, 2024
    Assignees: POSCO CO., LTD, NOROO COIL COATINGS CO., LTD.
    Inventors: Chang-Hoon Choi, Dong-Yun Kim, Min-Ho Jo, Jae-Duck Ko, Won-Ho Son, Jong-Hwa Kim
  • Patent number: 11935481
    Abstract: Provided is a display device, which includes: a reference voltage line formed along a circular outer line and configured to provide a reference voltage; a first reference voltage auxiliary line electrically connected to the reference voltage line and formed to be parallel with a predetermined interval; and a conductive line forming a contact with the reference voltage line and the first reference voltage auxiliary line and configured to provide the reference voltage to a cathode.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: March 19, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung Han Jo, Min Chae Kwak, Kyeong Hwa Kim, Mi Hae Kim, Kyong Hwan Oh, Su Mi Jang, Jae-Ho Choi
  • Publication number: 20240085282
    Abstract: There is provide a method for manufacturing analytical semiconductor samples by using an apparatus for manufacturing analytical semiconductor samples, which minimizes a feedback time by manufacturing a viewing surface that is environment-friendly and has a large area. The method comprising mounting the analytical semiconductor samples to a holder; discharging deionized (DI) water to an upper surface of a polishing plate through a DI water nozzle; grinding the analytical semiconductor samples with the upper surface of the polishing plat; determining whether a desired viewing surface of the analytical semiconductor samples has been acquired after the grinding of the analytical semiconductor samples; and transferring the analytical semiconductor samples to analyze the viewing surface of the ground analytical semiconductor samples based on a determination that the desired viewing surface of the analytical semiconductor samples has been acquired.
    Type: Application
    Filed: August 23, 2023
    Publication date: March 14, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min Chul JO, Sang Hyun PARK, Su Jin SHIN, Gil Ho GU, Dae Gon YU, So Yeon LEE, Yun Bin JEONG
  • Publication number: 20240069535
    Abstract: The present disclosure relates to a simulation apparatus for secondary battery production.
    Type: Application
    Filed: July 14, 2022
    Publication date: February 29, 2024
    Inventors: Shinkyu KANG, Min Yong KIM, Youngduk KIM, Nam Hyuck KIM, Su Ho JEON, Min Hee KWON, Sung Nam CHO, Hyeong Geun CHAE, Gyeong Yun JO, Moon Kyu JO, Kyungchul HWANG, Moo Hyun YOO, Han Seung KIM, Daewoon JUNG, Seungtae KIM, Junhyeok JEON
  • Publication number: 20200032080
    Abstract: Provided is a composition for surface treatment of a steel sheet, the composition having excellent resistance to an acid, such as sulfuric acid, and to a coated steel sheet to which the composition for surface treatment is applied, wherein the composition for surface treatment comprises 30-50% wt % of colloidal silica containing 5-20 nm-sized silica, 40-60% wt % of silane containing three or more alkoxy groups, 5-15 wt % of an acrylate-based organic monomer, 0.01-1 wt % of an acid, and 1-15 wt % of a solvent.
    Type: Application
    Filed: September 28, 2017
    Publication date: January 30, 2020
    Inventors: Chang-Hoon CHOI, Dong-Yun KIM, Min-Ho JO, Jae-Duck KO, Won-Ho SON, Jong-Hwa KIM
  • Publication number: 20190316240
    Abstract: Disclosed are a cold rolled steel sheet and a method for manufacturing same, the cold-rolled steel sheet: comprising, by wt %, 0.01% or less of C, 0.5% or less of Si, 0.1-0.5% of Mn, 0.1% or less of Al, 0.01% or less of P, 0.01% or less of S, 0.005% or less of N and 0.2-0.8% of Nb; comprising one or more of 0.5% or less of Sb, 3.0% or less of Cr, 1.0% or less of Mo and 0.5% or less of W; comprising the balance of Fe and inevitable impurities; and satisfying the following relation 1. [relation 1] 0.2?[Sb]/0.5+[Cr]/3.0+[Mo]/1.0+[W]/0.5?1.5 (Here, [Sb], [Cr], [Mo], and [W] respectively mean the amounts (wt %) of the corresponding elements contained.
    Type: Application
    Filed: December 11, 2017
    Publication date: October 17, 2019
    Inventors: Min-Ho JO, Jong-Hwa Kim
  • Publication number: 20180371565
    Abstract: A continuous self-brazing cold rolled steel sheet according to an embodiment of the present disclosure includes 0.02 wt % to 0.08 wt % of C, 0.03 wt % to 0.10 wt % of Mn, 0.10 wt % or less of Si (excluding 0 wt %), 0.005 wt % to 0.05 wt % of Al, 0.015 wt % or less of P (excluding 0 wt %), 0.01 wt % or less of S (excluding 0 wt %), 0.005 wt % or less of N (excluding 0 wt %), 0.0003 wt % to 0.0036 wt % of B, a remainder Fe, and other inevitable impurities, and satisfying Equations (1) and (2), in which an average crystal grain size is 8 ?m to 16 ?m. 0.15?([B]/10.81)/([Al]/26.98)??[Equation 1] 0.8?([B]/10.81)/([N]/14.01)?1.6??[Equation 2] (In Equations (1) and (2), [B], [Al] and [N] denote percent by weights of B, Al, and N.
    Type: Application
    Filed: December 22, 2016
    Publication date: December 27, 2018
    Inventors: Min Ho JO, Young-Kwang HONG
  • Patent number: 7324530
    Abstract: Provided is a routing method for determining a destination in a computer network having multiple interconnected nodes, the method for measuring packet delays among remotely located gateways and processing routing in application layers of the gateways using the packet delays. The routing method based on packet delay includes the steps of setting a re-routing interval and measuring one-way delays among gateways, exchanging the measured delays among the respective gateways and forming delay time tables, calculating an average one-way delay during the re-routing interval, and if a packet is received, applying the calculated average one-way delay to a predetermined algorithm and determining a path from a source gateway to a destination gateway, the path having the minimum delay. Therefore, an improved routing performance can be achieved in real time transmitting a packet by determining the minimum delay path to a destination by measuring packet delays among remotely located nodes in application layers thereof.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: January 29, 2008
    Assignee: Daewoo Educational Foundation
    Inventors: Min Ho Jo, Tae Hwa Kim, Hyo Gon Kim, Seung Wha Yoo, Hyoung Do Kim
  • Publication number: 20030091029
    Abstract: Provided is a routing method for determining a destination in a computer network having multiple interconnected nodes, the method for measuring packet delays among remotely located gateways and processing routing in application layers of the gateways using the packet delays. The routing method based on packet delay includes the steps of setting a re-routing interval and measuring one-way delays among gateways, exchanging the measured delays among the respective gateways and forming delay time tables, calculating an average one-way delay during the re-routing interval, and if a packet is received, applying the calculated average one-way delay to a predetermined algorithm and determining a path from a source gateway to a destination gateway, the path having the minimum delay. Therefore, an improved routing performance can be achieved in real time transmitting a packet by determining the minimum delay path to a destination by measuring packet delays among remotely located nodes in application layers thereof.
    Type: Application
    Filed: June 28, 2002
    Publication date: May 15, 2003
    Inventors: Min Ho Jo, Tae Hwa Kim, Hyo Gon Kim, Seung Wha Yoo, Hyoung Do Kim