Abstract: An address detection circuit comprises first to N-th address storage units suitable for storing an address, first to N-th calculation units each suitable for performing a counting operation when an address is stored in a corresponding address storage unit among the address storage units or the address stored in the corresponding address storage unit is inputted, a control unit suitable for sequentially storing an input address in the address storage units, and storing the input address in a selected address storage unit among the address storage units when of the address storage units each store an address, and a detection unit suitable for detecting an address, which is inputted a reference number of times or more, among the addresses stored in the address storage units, based on outputs of the calculation units.

Abstract: A latch circuit includes: first to Nth storage nodes, where N is an even number equal to or greater than 4; first to Nth pairs of transistors, each of which includes a PMOS transistor and an NMOS transistor coupled in series with each other through a corresponding storage node among the first to Nth storage nodes, wherein each of the first to Nth storage nodes is coupled with a gate of the NMOS transistor included in a previous one of the pairs of transistors and a gate of the PMOS transistor included in a next one of the pairs of transistors; and an initialization block suitable for initializing voltages of two or more nodes among the first to Nth storage nodes to a first level in response to an initialization signal.

Abstract: An address detection circuit comprises first to N-th address storage units suitable for storing an address, first to N-th calculation units each suitable for performing a counting operation when an address is stored in a corresponding address storage unit among the address storage units or the address stored in the corresponding address storage unit is inputted, a control unit suitable for sequentially storing an input address in the address storage units, and storing the input address in a selected address storage unit among the address storage units when of the address storage units each store an address, and a detection unit suitable for detecting an address, which is inputted a reference number of times or more, among the addresses stored in the address storage units, based on outputs of the calculation units.