Abstract: The present invention provides a display device and a manufacturing method thereof. The display device includes a gate line, a data line that is insulated from and crosses the gate line, a thin film transistor including a semiconductor layer and connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and a dummy drain electrode adjacent to a channel region of the thin film transistor. The dummy drain electrode is not connected to the pixel electrode.

Abstract: An organic thin film transistor substrate includes a substrate, a gate line on a surface of the substrate, a gate insulating layer insulating on the gate line, a data line on the gate insulating layer, an organic thin film transistor connected to the gate line and the data line, the organic thin film transistor including an organic semiconductor layer, a bank-insulating layer positioned at least in part on the data line, the bank-insulating layer including a wall portion which defines a pixel area, and a pixel electrode formed in the pixel area.

Abstract: An organic thin film transistor substrate for a display device includes a gate line, a data line insulated from the gate line, at least two organic thin film transistors, each of which is connected between the gate line and the data line, and both of which are commonly connected to a main drain electrode, and a pixel electrode connected to the main drain electrode.

Abstract: A manufacturing method for a thin film transistor array panel including forming a gate electrode, forming an insulating layer on the gate electrode, sequentially forming a lower conducting layer and a upper conducting layer on the insulating layer, etching the upper conducting layer to form a first source electrode and a first drain electrode, etching the lower conducting layer to form the second source electrode and the second drain electrode, over-etching the second source electrode and the second drain electrode, and forming an organic semiconductor between the second source electrode and the second drain electrode.

Abstract: A method for manufacturing a thin film transistor (“TFT”) array panel includes forming a gate electrode, forming source and drain electrodes insulated from the gate electrode, forming an organic semiconductor contacting the source and drain electrodes, spraying a solvent on the organic semiconductor, drying the solvent at room temperature, and annealing the organic semiconductor.

Abstract: A method for forming a contact of an organic active layer is provided. In this method, a transparent conductive oxide thin film is formed on a substrate, and a surface of the oxide thin film is activated by inducing a base —OH and an oxide —O. Then, the oxide thin film is washed with a hydrophobic material after activating the surface. A self-assembled monolayer is formed on the oxide thin film after washing, and an organic active layer is formed on the self-assembled monolayer. A method for manufacturing a flat panel display including formation of the contact, and an organic thin film transistor display panel and an organic light emitting diode display including the contact are also provided.

Abstract: A thin film transistor array panel according to an embodiment of the present invention includes a gate electrode, a source electrode and a drain electrode opposing each other and separated from each other on the gate electrode. An organic semiconductor is in contact with the source electrode and the drain electrode. A gate insulator is formed between the gate electrode and the organic semiconductor. A pixel electrode is connected to the drain electrode. A passivation member covers the organic semiconductor and includes a nonionic soluble polymer.

Abstract: The present invention provides an organic thin film transistor substrate and a method of manufacturing the same capable of uniformly forming the thickness of a gate insulating layer and a protective layer and preventing overflow of an organic semiconductive layer.

Abstract: A display device includes an insulation substrate, a source electrode and a drain electrode disposed on the insulation substrate and distanced from each other and including a channel area interposed therebetween, a wall exposing portions of the source electrode and the drain electrode, and defining an opening area surrounding the channel area, and an organic semiconductor layer covering the channel area, and comprising a first sub layer and a second sub layer having different grain sizes.

Abstract: An apparatus and method for accelerating an initial lock time of the DLL in a high rate double data rate (DDR) synchronous random access memory (SDRAM) is disclosed.

Abstract: An apparatus for receiving an external data strobe signal in a high-speed memory device to generate an internal data strobe signal used in a write operation therein, includes first buffering means, activated by an enable signal, for receiving the external data strobe signal having a series of pulses to output a first internal data strobe signal having a series of pulses, each pulse of the first internal data strobe signal corresponding to a rising edge of each pulse of the external data strobe signal, and second buffering means, activated by the enable signal, for receiving the external data strobe signal having a series of pulses to output a second internal data strobe signal having a series of pulses, each pulse of the second internal data strobe signal corresponding to a falling edge of each pulse of the external data strobe signal, wherein a delay to a corresponding pulse of the first internal data strobe signal from a rising edge of each pulse of the external data strobe signal is substantially identical

Abstract: A synchronous memory device includes: a plurality of pipelatch circuits storing data as pull-up and pull-down signals, transferring the stored data to pull-up and pull-down lines and producing initialization signals to initialize the pull-up and pull-down lines in response to a pipe count signal; common pull-up and pull-down lines coupled to the pull-up and pull-down lines in response to the pipe count signal and the initialization signals; initialization unit for supplying a power supply to the pull-up and pull-down lines in response to a reset signal, the pipe count signal and the initialization signals; an output buffer outputting the data transferred by the common pull-up and pull-down lines; and a precharging unit for precharging the pull-up and pull-down lines and the common pull-up and pull-down lines in response to an output signal from the output buffer, wherein the common pull-up and pull-down lines is precharged to a ground voltage level.

Abstract: A memory device for storing multi-data comprises an input level detector for receiving data through n input terminals and selecting one of 2.sup.n output terminals corresponding to the data inputted to the input terminals; a word line switching unit for outputting one of 2.sup.n reference voltages corresponding to the outputs from the input level detector; and a word line driver for receiving the output from the word line switching unit and transferring it to the corresponding word line of the memory device.