Abstract: The disclosure provides a restart control device and a restart control method. The restart control device is disposed in an electronic device. The electronic device includes a keyboard and a restart button. At least one assigned key of a plurality of keys of the keyboard is set. The restart control device determines whether the at least one assigned key is pressed, and determines whether the restart button is pressed. When determining that the restart button is pressed and the at least one assigned key is pressed, the restart control device provides a restart control signal to cause the electronic device to perform a restart operation. The disclosure can prevent an unnecessary restart operation due to a single restart button being mistyped.

Abstract: Provided are an electrode plate and a battery cell of a wound lithium-ion battery and a method for manufacturing same. The electrode plate comprises an electrode plate body and at least two groups of tabs arranged on the electrode plate body, with each group of tabs including multiple tabs, wherein the multiple tabs have equal intervals therebetween, and the widths of the multiple tabs are successively increased by 2??t, with ?t being the sum of the thicknesses of a positive electrode plate, a negative electrode plate and two layers of a separation film of the battery cell of the lithium-ion battery. The present invention can avoid the problem in the prior art of burrs on an electrode plate due to secondary die-cutting, and can reduce the possibility of self-discharge of the battery. Since the body of each tab is completely coated with an electrode material, the energy density is high, thereby improving the safety of the battery.

Abstract: Provided are an electrode plate and a battery cell of a wound lithium-ion battery and a method for manufacturing same. The electrode plate comprises an electrode plate body and at least two groups of tabs arranged on the electrode plate body, with each group of tabs including multiple tabs, wherein the multiple tabs have equal intervals therebetween, and the widths of the multiple tabs are successively increased by 2??t, with ?t being the sum of the thicknesses of a positive electrode plate, a negative electrode plate and two layers of a separation film of the battery cell of the lithium-ion battery. The present invention can avoid the problem in the prior art of burrs on an electrode plate due to secondary die-cutting, and can reduce the possibility of self-discharge of the battery. Since the body of each tab is completely coated with an electrode material, the energy density is high, thereby improving the safety of the battery.

Abstract: A catalyst for producing light aromatics with heavy aromatics, a method for preparing the catalyst, and a use thereof are disclosed. The catalyst comprises a carrier, component (1), and component (2), wherein component (1) comprises one metal element or more metal elements selected from a group consisting of Pt, Pd, Ir, and Rh, and component (2) comprises one metal element or more metal elements selected from a group consisting of IA group, IIA group, IIIA group, IVA group, IB group, IIB group, IIIB group, IVB group, VB group, VIB group, VIIB group, La group, and VIII group other than Pt, Pd, Ir, and Rh. The catalyst can be used for producing light aromatics with heavy aromatics, whereby heavy aromatics hydrogenation selectivity and light aromatics yield can be improved.

Abstract: The disclosure provides a restart control device and a restart control method. The restart control device is disposed in an electronic device. The electronic device includes a keyboard and a restart button. At least one assigned key of a plurality of keys of the keyboard is set. The restart control device determines whether the at least one assigned key is pressed, and determines whether the restart button is pressed. When determining that the restart button is pressed and the at least one assigned key is pressed, the restart control device provides a restart control signal to cause the electronic device to perform a restart operation. The disclosure can prevent an unnecessary restart operation due to a single restart button being mistyped.

Abstract: A catalyst for producing light aromatics with heavy aromatics, a method for preparing the catalyst, and a use thereof are disclosed. The catalyst comprises a carrier, component (1), and component (2), wherein component (1) comprises one metal element or more metal elements selected from a group consisting of Pt, Pd, Ir, and Rh, and component (2) comprises one metal element or more metal elements selected from a group consisting of IA group, IIA group, IIIA group, IVA group, IB group, IIB group, IIIB group, IVB group, VB group, VIB group, VIIB group, La group, and VIII group other than Pt, Pd, Ir, and Rh. The catalyst can be used for producing light aromatics with heavy aromatics, whereby heavy aromatics hydrogenation selectivity and light aromatics yield can be improved.

Abstract: An electronic apparatus and a method for detecting status of keys thereof are provided. The electronic apparatus comprises a key module, a key control circuit, a conversion circuit with calibration mechanism and a processor. The key control circuit detects whether any of keys in the key module is pressed. If the detection result is affirmative, the press status of each of the keys is scanned by the key control circuit to obtain a coarse scan result. The conversion circuit with calibration mechanism is configured to perform the other system function of the electronic apparatus. When the processor determines that at least one of the keys is not pressed according the coarse scan result, the conversion circuit with calibration mechanism is switched to assist a re-scan operation of the press status of the at least one of the keys.

Abstract: An electronic apparatus and a method for detecting status of keys thereof are provided. The electronic apparatus comprises a key module, a key control circuit, a conversion circuit with calibration mechanism and a processor. The key control circuit detects whether any of keys in the key module is pressed. If the detection result is affirmative, the press status of each of the keys is scanned by the key control circuit to obtain a coarse scan result. The conversion circuit with calibration mechanism is configured to perform the other system function of the electronic apparatus. When the processor determines that at least one of the keys is not pressed according the coarse scan result, the conversion circuit with calibration mechanism is switched to assist a re-scan operation of the press status of the at least one of the keys.

Abstract: A solution is provided to flexibly choose a combination of flash memory devices to reduce the overall cost of the flash memory devices or increase the overall utilization of the flash memory devices, while satisfying the capacity requirements for the flash memory devices in a system design, wherein a decoding unit is used for determining which flash memory devices will be accessed and re-mapping incoming serial addressing bits, for accessing one flash memory device, into an outgoing serial addressing bits for accessing another flash memory device.

Abstract: A flash memory storage system includes a flash memory, a host and a controller is provided. The controller couples to the host and the flash memory, and restricts the host to access the flash memory according to a state of the host. When the host is in a booting state or in a resetting state, the controller allows the host to access the flash memory. After the host completes a booting process or a resetting process, the controller restricts the host to access the flash memory so as to protect a data stored by the flash memory. Besides, a data protection method for which applied to the above-mentioned storage system is also provided in the present invention.

Abstract: A solution is provided to flexibly choose a combination of flash memory devices to reduce the overall cost of the flash memory devices or increase the overall utilization of the flash memory devices, while satisfying the capacity requirements for the flash memory devices in a system design, wherein a decoding unit is used for determining which flash memory devices will be accessed and re-mapping incoming serial addressing bits, for accessing one flash memory device, into an outgoing serial addressing bits for accessing another flash memory device.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.