Patents by Inventor Min-Hsin HSIEH

Min-Hsin HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9703919
    Abstract: A method of generating a set of defect candidates for a wafer is disclosed. The wafer comprises at least one die manufactured according to a mask, and the mask being prepared by combining a plurality of layout areas. The method includes receiving an initial defect information from a wafer scanning device indicating potential defects of a semiconductor wafer and determining a boundary region on the semiconductor wafer. The method further includes creating an exclusion region from the boundary region, the exclusion region having a first set of defects in the potential defects of the semiconductor wafer, and creating filtered defect information by removing the first set of defects from the initial defect information.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: July 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Hsin Hsieh, Tsung-Hsien Lee
  • Publication number: 20150261908
    Abstract: A method of generating a set of defect candidates for a wafer is disclosed. The wafer comprises at least one die manufactured according to a mask, and the mask being prepared by combining a plurality of layout areas. The method includes receiving an initial defect information from a wafer scanning device indicating potential defects of a semiconductor wafer and determining a boundary region on the semiconductor wafer. The method further includes creating an exclusion region from the boundary region, the exclusion region having a first set of defects in the potential defects of the semiconductor wafer, and creating filtered defect information by removing the first set of defects from the initial defect information.
    Type: Application
    Filed: May 28, 2015
    Publication date: September 17, 2015
    Inventors: Min-Hsin HSIEH, Tsung-Hsien LEE
  • Patent number: 9057965
    Abstract: A method of generating a set of defect candidates for a wafer includes generating a filtration area according to a graph operation of one or more of a plurality of layout areas. The wafer includes at least one die manufactured according to a mask, and the mask is prepared by combining the plurality of layout areas. The method further includes generating the set of defect candidates by omitting a subset of initial defect candidates having positions within the filtration area.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: June 16, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Hsin Hsieh, Tsung-Hsien Lee
  • Publication number: 20140157213
    Abstract: A method of generating a set of defect candidates for a wafer includes generating a filtration area according to a graph operation of one or more of a plurality of layout areas. The wafer includes at least one die manufactured according to a mask, and the mask is prepared by combining the plurality of layout areas. The method further includes generating the set of defect candidates by omitting a subset of initial defect candidates having positions within the filtration area.
    Type: Application
    Filed: December 3, 2012
    Publication date: June 5, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Hsin HSIEH, Tsung-Hsien LEE