Abstract: A semiconductor device includes parallel channel members, a gate structure, source/drain features, a silicide layer, and a source/drain contact. The parallel channel members are spaced apart from one another. The gate structure is wrapping around the channel members. The source/drain features are disposed besides the channel members and at opposite sides of the gate structure. The silicide layer is disposed on and in direct contact with the source/drain features. The source/drain contact is disposed on the silicide layer, wherein the source/drain contact includes a first source/drain contact and a second source/drain contact stacked on the first source/drain contact, and the second source/drain contact is separate from the silicide layer by the first source/drain contact.

Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a front side of a substrate. The method also includes forming a gate structure surrounding the nanostructures. The method also includes forming a source/drain structure beside the gate structure. The method also includes forming a trench though the substrate from a back side of the substrate. The method also includes forming a first silicide layer in contact with the source/drain structure. The method also includes forming a second silicide layer over the first silicide layer and the sidewalls of the trench. The method also includes depositing a first conductive material over the second silicide layer. The method also includes etching back the first conductive material. The method also includes etching back the second silicide layer. The method also includes depositing a second conductive material in the trench.

Abstract: A method for forming a semiconductor device includes followings. A transistor is formed, and the transistor is embedded in a dielectric layer and disposed over a semiconductor substrate. A first gate cutting process is performed to form a first opening in the dielectric layer. An insulator post is formed in the first opening. A second gate cutting process is performed to form a second opening in the dielectric layer. A power via is formed in the second opening. A conductor is formed, wherein the conductor is embedded in the semiconductor substrate, and the conductor is located under and electrically connected to the power via.

Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.

Abstract: A semiconductor device and a method of manufacturing thereof are provided. The semiconductor device comprises a gate stack, source/drain regions, and a source/drain contact via. The gate stack is disposed on a substrate. The source/drain regions are disposed on the substrate and located at opposite sides of the gate stack. The source/drain contact via penetrates through the substrate and is electrically connected to a first source/drain region among the source/drain regions. The source/drain contact vias comprise a first conductor and a second conductor disposed on the first conductor. The first conductor comprises a silicide layer and a first metallic portion. The second conductor comprises a glue layer and a second metallic portion. The first metallic portion is spaced apart from the second metallic portion by the glue layer.

Abstract: A device includes a substrate, a vertical stack of nanostructure channels over the substrate, a gate structure wrapping around the nanostructure channels, and a source/drain region on the substrate. The device further includes a source/drain contact in contact with the source/drain region. The source/drain contact includes a core layer of a first material. A source/drain via is over and in contact with the source/drain contact. The source/drain via is the first material. A gate via is over and in electrical connection with the gate structure. The gate via is the first material.

Abstract: A method for assessing drug-resistant microorganism includes the following steps. A model establishing step is performed so as to obtain an antibiotic resistance assessing classifier. A test sample is provided. A sample pre-processing step is performed so as to obtain a processed sample. An analysis step is performed so as to obtain a target mass spectrum data. A spectrum pre-processing step is performed so as to obtain a normalized target mass spectrum data. A feature extraction step is performed so as to obtain a spectrum feature. An assessing step is performed, wherein the spectrum feature is analyzed by the antibiotic resistance assessing classifier so as to output an assessed result of drug-resistant microorganism, and the assessed result of drug-resistant microorganism is for assessing whether the test microorganism is a drug-resistant microorganism or not.

Abstract: In a semiconductor structure, a first conductive feature is formed in a trench by PVD and a glue layer is then deposited on the first conductive feature in the trench before CVD deposition of a second conductive feature there-over. The first conductive feature acts as a protection layer to keep silicide from being damaged by later deposition of metal or a precursor by CVD. The glue layer extends along the extent of the sidewall to enhance the adhesion of the second conductive features to the surrounding dielectric layer.