Patents by Inventor Min-Huang Wu

Min-Huang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250052806
    Abstract: Systems and methods are provided for testing sockets, such as but not limited to CPU and GPU sockets. Systems and methods disclosed herein utilize a test card that has a test component and an adaptor Printed Circuit Board. The adaptor Printed Circuit Board (PCB) is configured to connect with a corresponding socket type on a motherboard and serves as an interface between the test component and a socket of the corresponding socket type. The test component includes logic that simulates a test function to test the socket. By connecting the test card to a socket using the adaptor PCB, the socket can be tested by simulating the test function on the test card.
    Type: Application
    Filed: August 9, 2023
    Publication date: February 13, 2025
    Inventors: MIN-HUANG WU, Heriberto Castillo Velez
  • Patent number: 11493549
    Abstract: An apparatus is provided for testing a PCIe interface on a printed circuit assembly. The apparatus can include a plurality of electrical contacts to couple to a PCIe interface of the printed circuit assembly, wherein a respective electrical contact corresponds to a pin of the PCIe interface. The apparatus can also include a plurality of resistors. Each resistor is coupled between two adjacent electrical contacts. At least one electrical contact corresponds to a ground, power, or not connected (NC) pin of the PCIe interface, thereby allowing a loopback test to determine connectivity between the pins of the PCIe interface and the printed circuit assembly.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: November 8, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Min-Huang Wu
  • Publication number: 20210389367
    Abstract: An apparatus is provided for testing a PCIe interface on a printed circuit assembly. The apparatus can include a plurality of electrical contacts to couple to a PCIe interface of the printed circuit assembly, wherein a respective electrical contact corresponds to a pin of the PCIe interface. The apparatus can also include a plurality of resistors. Each resistor is coupled between two adjacent electrical contacts. At least one electrical contact corresponds to a ground, power, or not connected (NC) pin of the PCIe interface, thereby allowing a loopback test to determine connectivity between the pins of the PCIe interface and the printed circuit assembly.
    Type: Application
    Filed: June 16, 2020
    Publication date: December 16, 2021
    Inventor: Min-Huang Wu