Abstract: A method includes forming an interfacial layer over a substrate; forming a quasi-antiferroelectric (QAFE) layer over the interfacial layer, in which forming the QAFE layer comprises performing an atomic layer deposition (ALD) cycle, and the ALD cycle includes performing a first sub-cycle for X time(s), in which the first sub-cycle comprises providing a Zr-containing precursor; performing a second sub-cycle for Y time(s), in which the second sub-cycle comprises providing a Hf-containing precursor; and performing a third sub-cycle for Z time(s), in which the third sub-cycle comprises providing a Zr-containing precursor, and in which X+Z is at least three times Y; and forming a gate electrode over the QAFE layer.

Abstract: An active stylus having physical writing function includes a tip shell including a first opening and a second opening, a first electrode including a first end protruded through the first opening of the tip shell and including a second end protruded through the second opening of the tip shell and entered a main body housing of the active stylus, wherein the first electrode includes conductive material. The tip shell includes non-conductive material. The first end of the first electrode is configured to leave colored traces on an object by physical friction caused between the first end of the first electrode and the object.

Abstract: An integrated circuit device includes a substrate and a memory device. The memory device is over the substrate. The memory device includes a bottom electrode, a dielectric layer, an antiferroelectric layer, and a top electrode. The dielectric layer is over the bottom electrode. The antiferroelectric layer is over the dielectric layer. The top electrode is over the antiferroelectric layer.

Abstract: A method includes forming a semiconductor layer over a substrate; depositing a first ferroelectric layer over a channel region of the semiconductor layer; depositing a first dielectric layer over the first ferroelectric layer; depositing a second ferroelectric layer over the first dielectric layer; depositing a gate metal layer over the second ferroelectric layer; patterning the gate metal layer, the second ferroelectric layer, the first dielectric layer, and the first ferroelectric layer to form a gate structure; and forming source/drain regions in the semiconductor layer and on opposite sides of the gate structure.

Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, and source/drain regions in the substrate and on opposite sides of the gate structure. The gate structure includes an interfacial layer, a quasi-antiferroelectric (QAFE) layer over the interfacial layer, and a gate electrode over the QAFE layer. The QAFE layer includes Hf1?xZrxO2, in which x is greater than 0.5 and is lower than 1.

Abstract: A method includes forming an interfacial layer over a substrate; forming a quasi-antiferroelectric (QAFE) layer over the interfacial layer, in which forming the QAFE layer comprises performing an atomic layer deposition (ALD) cycle, and the ALD cycle includes performing a first sub-cycle for X time(s), in which the first sub-cycle comprises providing a Zr-containing precursor; performing a second sub-cycle for Y time(s), in which the second sub-cycle comprises providing a Hf-containing precursor; and performing a third sub-cycle for Z time(s), in which the third sub-cycle comprises providing a Zr-containing precursor, and in which X+Z is at least three times Y; and forming a gate electrode over the QAFE layer.

Abstract: A semiconductor device includes a source and a drain and a channel disposed between the source and the drain, a first gate dielectric layer disposed on the channel, a first gate electrode disposed on the first gate dielectric layer, a second gate dielectric layer disposed on the first gate electrode, and a second gate electrode disposed on the second gate dielectric layer. The second gate dielectric layer is made of a ferroelectric material. A first area of a bottom surface of the first gate electrode which is in contact with the first gate dielectric layer where the is greater than a second area of a bottom surface of the second gate dielectric layer which is in contact with the first gate electrode.

Abstract: A Heterojunction with Intrinsic Thin layer (HIT) solar cell has a crystalline Si substrate, an intrinsic amorphous Si layer, a doped amorphous Si layer, a transparent conductive layer and two electrode layers. The intrinsic amorphous Si layer disposed between the doped amorphous Si layer and the crystalline silicon substrate contacts the doped amorphous Si layer and the crystalline silicon substrate. Each of the intrinsic amorphous Si layer and the doped amorphous Si layer has the thickness less than 50 nm. The intrinsic amorphous Si layer and the doped amorphous Si layer are both made by electron beam evaporation. The transparent conductive layer is formed on the doped amorphous Si layer. The two electrode layers are formed on the transparent conductive layer and the crystalline silicon substrate respectively. The crystalline silicon substrate is disposed between the two electrode layers.

Abstract: A semiconductor device includes a source and a drain and a channel disposed between the source and the drain, a first gate dielectric layer disposed on the channel, a first gate electrode disposed on the first gate dielectric layer, a second gate dielectric layer disposed on the first gate electrode, and a second gate electrode disposed on the second gate dielectric layer. The second gate dielectric layer is made of a ferroelectric material. A first area of a bottom surface of the first gate electrode which is in contact with the first gate dielectric layer where the is greater than a second area of a bottom surface of the second gate dielectric layer which is in contact with the first gate electrode.

Abstract: The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a substrate; a gate stack over the substrate. The gate stack includes a ferroelectric layer; a first dielectric material layer; and a first conductive layer. One of the first dielectric material layer and the ferroelectric layer is electrically charged to form a charged layer with fixed charge. The semiconductor device further includes source and drain features formed on the substrate and disposed on sides of the gate stack.

Abstract: A Tunnel Field-Effect Transistor (TFET) includes a source region in a semiconductor substrate, and a drain region in the semiconductor substrate. The source region and the drain region are of opposite conductivity types. The TFET further includes a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack. The gate stack includes a gate dielectric over the semiconductor substrate, and a ferroelectric layer over the gate dielectric.

Abstract: The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a substrate; a gate stack over the substrate. The gate stack includes a ferroelectric layer; a first dielectric material layer; and a first conductive layer. One of the first dielectric material layer and the ferroelectric layer is electrically charged to form a charged layer with fixed charge. The semiconductor device further includes source and drain features formed on the substrate and disposed on sides of the gate stack.

Abstract: A Tunnel Field-Effect Transistor (TFET) includes a source region in a semiconductor substrate, and a drain region in the semiconductor substrate. The source region and the drain region are of opposite conductivity types. The TFET further includes a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack. The gate stack includes a gate dielectric over the semiconductor substrate, and a ferroelectric layer over the gate dielectric.

Abstract: A Tunnel Field-Effect Transistor (TFET) includes a source region in a semiconductor substrate, and a drain region in the semiconductor substrate. The source region and the drain region are of opposite conductivity types. The TFET further includes a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack. The gate stack includes a gate dielectric over the semiconductor substrate, and a ferroelectric layer over the gate dielectric.

Abstract: A Tunnel Field-Effect Transistor (TFET) includes a source region in a semiconductor substrate, and a drain region in the semiconductor substrate. The source region and the drain region are of opposite conductivity types. The TFET further includes a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack. The gate stack includes a gate dielectric over the semiconductor substrate, and a ferroelectric layer over the gate dielectric.

Abstract: A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase change layer, and the ring via takes the center via as a center. A heating electrode within the center via performs Joule heating of the phase change layer, and the contact area between the phase change layer and the heating electrode is reduced by controlling the thickness of the phase change layer. Furthermore, a second electrode within the ring via dissipates the heat transmitted to the contact interface between the phase change layers, so as to avoid transmitting the heat to the etching boundary at the periphery of the phase change layer.

Abstract: A phase change memory (PCM) cell fabricated by etching a tapered structure into a phase change layer, and planarizing a dielectric layer on the phase change layer until a tip of the tapered structure is exposed for contacting a heating electrode. Therefore, the area of the exposed tip of the phase change layer is controlled to be of an extremely small size, the contact area between the phase change layer and the heating electrode is reduced, thereby lowering the operation current.

Abstract: The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate.

Abstract: A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase change layer, and the ring via takes the center via as a center. A heating electrode within the center via performs Joule heating of the phase change layer, and the contact area between the phase change layer and the heating electrode is reduced by controlling the thickness of the phase change layer. Furthermore, a second electrode within the ring via dissipates the heat transmitted to the contact interface between the phase change layers, so as to avoid transmitting the heat to the etching boundary at the periphery of the phase change layer.

Abstract: A strained germanium field effect transistor (FET) and method of fabricating the same is related to the strained Ge field effect transistor with a thin and pure Ge layer as a carrier channel. The pure Ge layer with the thickness between 1 nm and 10 nm is formed between an unstrained substrate and a gate insulation layer, and directly contacts with the unstrained substrate. The gate is disposed on the gate insulation layer. The germanium layer is used as a carrier transport channel of the strained Ge FET to improve the drive current and the carrier mobility, and to increase the devices performance effectively. Furthermore, a Si protective layer with extremely thin thickness can be deposed between and directly contacts with the gate insulation layer and the pure Ge layer.