Patents by Inventor Min-Hwa Chi

Min-Hwa Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10622463
    Abstract: At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a tall fin having a plurality of epitaxial regions. A first fin of a transistor is formed. The first fin comprising a first portion comprising silicon, a second portion comprising silicon germanium and a third portion comprising silicon. A gate structure above the third portion is formed. An etching process is performed for removing the silicon germanium of the second portion that is not below the gate structure. A first epitaxy region is formed above the first portion. A second epitaxy region is formed vertically aligned with the first epitaxy region and above the silicon germanium of the second portion that is below the gate structure.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Min-Hwa Chi, Jinping Liu
  • Patent number: 10572380
    Abstract: A flash memory device includes a substrate, an electrode layer on a portion of the substrate, the electrode layer being a work function adjusting layer or a metal silicide layer, and a memory cell. The memory cell includes a channel structure on the electrode layer and having, from the inside to the outside in this order, a channel layer in contact with the electrode layer, a tunneling insulator layer surrounding the channel layer, a charge trapping layer surrounding the tunneling insulator layer, and a barrier layer surrounding the charge trapping layer, and a plurality of gate structures surrounding the channel structure along an axial direction of the channel structure. The flash memory device may be formed on a dielectric layer, and its fabrication process is thus compatible with back end of line processes.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 25, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Shan Rong Li, Min-Hwa Chi, Sheng Fen Chiu
  • Publication number: 20200006654
    Abstract: Non-volatile memory and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming a first conductive layer on the base substrate; forming an interlayer dielectric layer on the first conductive layer; forming a plurality of through holes exposing the first conductive layer in the interlayer dielectric layer; forming a catalyst layer on at least one of sidewall surfaces and bottom surfaces of the through holes; forming a carbon nanotube layer in the through holes by a catalytic chemical vapor deposition process; and forming a second conductive layer on the carbon nanotube layer and a portion of the interlayer dielectric layer.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Inventors: Min-Hwa CHI, Zhong Shan HONG, Zhan YING
  • Patent number: 10483283
    Abstract: A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: November 19, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Shan Rong Li, Min-hwa Chi, Sheng Fen Chiu
  • Patent number: 10475899
    Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Julien Frougier, Hui Zang, Min-hwa Chi
  • Publication number: 20190326436
    Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.
    Type: Application
    Filed: June 6, 2019
    Publication date: October 24, 2019
    Inventors: Min-hwa CHI, Ajey JACOB, Abhijeet PAUL
  • Patent number: 10438955
    Abstract: Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one of a portion of the hard masks; forming sacrificial pillars over the substrate; forming sacrificial gates, wherein at least one sacrificial gate contacts at least one sacrificial pillar; growing an epitaxial layer between the at least one sacrificial gate and the at least one sacrificial pillar; starting a RMG process on the sacrificial gates; etching to remove the sacrificial pillars and form pillar openings; and completing the RMG process to fill the pillar openings and the gate openings with a metal.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Min-hwa Chi
  • Publication number: 20190296108
    Abstract: A device includes a first gate structure positioned above an active region defined in a semiconducting substrate. A first spacer is positioned adjacent the first gate structure. First conductive source/drain contact structures are positioned adjacent the first gate structure and separated from the first gate structure by the first spacer. A first recessed portion of the first conductive source/drain contact structures is positioned at a first axial position along the first gate structure. A second recessed portion of the first conductive source/drain contact structures is positioned at a second axial position along the gate structure. A dielectric cap layer is positioned above the first and second recessed portions. A first conductive contact contacts the first gate structure in the first axial position. The dielectric cap layer above the first recessed portion is positioned adjacent the first conductive contact.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Inventors: Hui Zang, Min-Hwa Chi
  • Patent number: 10396155
    Abstract: A method includes forming a device above an active region defined in a semiconducting substrate. The device includes a first gate structure, a first spacer formed adjacent the first gate structure, and first conductive source/drain contact structures positioned adjacent the first gate structure and separated from the first gate structure by the first spacer. A first portion of the first conductive source/drain contact structures is recessed at a first axial position along the first gate structure to define a first cavity. A second portion of the first conductive source/drain contact structures is recessed at a second axial position along the gate structure to define a second cavity. A dielectric cap layer is formed in the first and second cavities. A first conductive contact contacting the first gate structure in the first axial position is formed.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Min-Hwa Chi
  • Patent number: 10388790
    Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min-hwa Chi, Ajey Jacob, Abhijeet Paul
  • Publication number: 20190237478
    Abstract: A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current.
    Type: Application
    Filed: April 9, 2019
    Publication date: August 1, 2019
    Inventors: Shan Rong LI, Min-hwa CHI, Sheng Fen CHIU
  • Patent number: 10347740
    Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xusheng Wu, Min-hwa Chi, Edmund Kenneth Banghart
  • Patent number: 10332834
    Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chun Yu Wong, Jagar Singh, Ashish Baraskar, Min-hwa Chi
  • Patent number: 10297609
    Abstract: A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 21, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Shan Rong Li, Min-hwa Chi, Sheng Fen Chiu
  • Patent number: 10290634
    Abstract: A multi-Vt FinFET includes a semiconductor substrate, multiple first fins coupled to the semiconductor substrate having a first fin pitch, and multiple second fins coupled to the semiconductor substrate having a second fin pitch larger than the first fin pitch. The semiconductor structure further includes transistor(s) on the multiple first fins, and transistor(s) on the multiple second fins, a threshold voltage of the transistor(s) on the multiple second fins being higher than that of the transistor(s) on the multiple first fins.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wen Pin Peng, Min-hwa Chi
  • Patent number: 10290654
    Abstract: Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Manfred Eller, Min-hwa Chi
  • Patent number: 10276390
    Abstract: A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Min-hwa Chi, Meixiong Zhao, Kuniko Kikuta
  • Publication number: 20190123160
    Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.
    Type: Application
    Filed: November 14, 2018
    Publication date: April 25, 2019
    Inventors: Ruilong Xie, Andreas Knorr, Julien Frougier, Hui Zang, Min-hwa Chi
  • Patent number: 10269811
    Abstract: FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality of source/drain regions within the substrate adjacent to each of the gates; a dielectric disposed between each gate and the plurality of source/drain regions adjacent to each gate; a dielectric capping layer disposed on a first one of the at least two gates, wherein no dielectric capping layer is disposed on a second one of the at least two gates; and a local interconnect electrically connected to the second one of the at least two gates, wherein the dielectric capping layer disposed on the first one of the at least two gates prevents an electrical connection between the local interconnect and the first one of the at least two gates.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min-hwa Chi, Hui Zang
  • Patent number: 10243059
    Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: March 26, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Srikanth Balaji Samavedan, Manfred Eller, Min-hwa Chi, Hui Zang