Abstract: Provided is a display device, which includes: a reference voltage line formed along a circular outer line and configured to provide a reference voltage; a first reference voltage auxiliary line electrically connected to the reference voltage line and formed to be parallel with a predetermined interval; and a conductive line forming a contact with the reference voltage line and the first reference voltage auxiliary line and configured to provide the reference voltage to a cathode.

Abstract: A timing controller that includes a noise detection circuit and a setting control unit. The noise detection circuit includes a detection unit and a reset signal generating unit. The detection unit outputs a detection signal having a first logic level based on at least one of a plurality of reference data toggling asynchronous with a clock signal. The reset signal generating unit outputs a reset signal having a second logic level based on the detection signal. The setting control unit stores setting data and initializes the setting data in response to the reset signal having the first logic level, and the setting data are used to process red, green and blue (RGB) image data.

Abstract: The display device includes a driving circuit and a panel. The driving circuit is configured to generate a source output enable signal having at least one pulse during one horizontal scanning period in response to a mode signal and configured to generate a source driving signal by latching an image data in response to the source output enable signal. The driving circuit is further configured to generate an internal horizontal synchronization signal in response to the source output enable signal and configured to generate a gate driving signal in response to the internal horizontal synchronization signal. The panel is configured to display the image data in response to the gate driving signal and the source driving signal.

Abstract: A timing controller that includes a noise detection circuit and a setting control unit. The noise detection circuit includes a detection unit and a reset signal generating unit. The detection unit outputs a detection signal having a first logic level based on at least one of a plurality of reference data toggling asynchronous with a clock signal. The reset signal generating unit outputs a reset signal having a second logic level based on the detection signal. The setting control unit stores setting data and initializes the setting data in response to the reset signal having the first logic level, and the setting data are used to process red, green and blue (RGB) image data.

Abstract: The display device includes a driving circuit and a panel. The driving circuit is configured to generate a source output enable signal having at least one pulse during one horizontal scanning period in response to a mode signal and configured to generate a source driving signal by latching an image data in response to the source output enable signal. The driving circuit is further configured to generate an internal horizontal synchronization signal in response to the source output enable signal and configured to generate a gate driving signal in response to the internal horizontal synchronization signal. The panel is configured to display the image data in response to the gate driving signal and the source driving signal.

Abstract: Display panel driving circuits and methods of driving a display panel with first video data and second video data include determining a starting position and a stopping position of the first video data if the first video data is window data and reducing the size of the first video data if the first video data is full screen data. Alternating lines of a first portion of the display panel and a second portion of the display panel are driven with the reduced size first video data and the second video data so as to display the reduced size first video data in the first portion of the display panel and the second video data in the second portion of the display panel if the first video data is full screen data.

Abstract: Display panel driving circuits and methods of driving a display panel with first video data and second video data include determining a starting position and a stopping position of the first video data if the first video data is window data and reducing the size of the first video data if the first video data is full screen data. Alternating lines of a first portion of the display panel and a second portion of the display panel are driven with the reduced size first video data and the second video data so as to display the reduced size first video data in the first portion of the display panel and the second video data in the second portion of the display panel if the first video data is full screen data.

Abstract: A merged memory and logic (MML) integrated circuit includes a memory block having a plurality of memory banks, each of which is independently controlled by row address strobe signals, column address strobe signals and write enable signals. A logic block is connected to the memory block and generates an independent row address strobe signal, column address strobe signal and write enable signal for each of the plurality of memory banks. The memory block may also comprise a controller that independently controls each of the memory banks. The controller is connected between the logic block and the plurality of memory banks to receive the independent row address strobe signal, column address strobe signal and write enable signal for each of the plurality of memory banks from the logic block. Accordingly, high speed operation and control of memory banks in an MML integrated circuit may be provided.