Abstract: A display device includes a compensation value determiner which generates final compensation values for an input image, a timing controller which receives input grayscales of the input image and generate output grayscales by applying the final compensation values to the input grayscales, and a pixel unit which displays an output image corresponding to the output grayscales using pixels. The compensation value determiner determines weights based on display frequencies, display brightnesses, and the input grayscales, the compensation value determiner determines compensation values based on the display frequencies and positions of the pixels, and the compensation value determiner generates the final compensation values by applying the weights to the compensation values.

Abstract: A storage device may include: a plurality of memory dies; and a memory controller for receiving a first read request from a first function, controlling at least one memory die to perform a read operation according to the first read request, and controlling, when receiving a second read request from a second function in the course of the read operation according to the first read request, the at least one memory die to suspend the read operation according to the first read request and to perform a read operation according to the second read request based on a result obtained by comparing performance requirement information of the second function with residual time information of the second read request, which is determined according to a performance degree of the read operation being performed according to the first read request.

Abstract: The present disclosure relates to a memory controller and a method of operating the memory controller. The memory controller controlling a memory device including a plurality of planes includes a central processing unit (CPU) generating a command corresponding to a request from a host, a command queue storing the command, counter logic assigning to the command, number information corresponding to an order in which the command is generated and flag information indicating a level at which an operation corresponding to the command is performed, and a command queue controller controlling the command queue to transfer the command stored in the command queue to one of the plurality of planes corresponding to the command on the basis of the number information and the flag information.

Abstract: A storage device includes a memory device and a memory controller. The memory device stores a history read table including root bit information, read voltage information, and error bit information on each of a plurality of memory blocks, and performs a read operation of reading data stored in the plurality of memory blocks based on the history read table. When the read operation fails, a memory controller changes a level of a read voltage, and controls the memory device to perform a read retry operation of retrying the read operation by using the changed read voltage. When the read retry operation passes, the memory controller determines whether the history read table is to be updated by comparing the root bit information of the read retry operation with the root bit information of the history read table.

Abstract: A data storage device including a memory device and a memory controller is disclosed. The memory controller including a super block includes a parity controller in communication with a memory device including a plurality of pages and configured to generate a first parity using data to be written to a first group of pages among the plurality of pages, and generate a second parity using data to be written to a second group of pages among the plurality of pages, a write operation controller configured to control the memory device to store the first parity and the second parity, and an error correction circuitry coupled to apply the first parity and the second parity to correct at least one of the plurality of pages arranged to belong to the first group of pages and the second group of pages.

Abstract: A storage device includes a memory device and a memory controller. The memory device stores a history read table including root bit information, read voltage information, and error bit information on each of a plurality of memory blocks, and performs a read operation of reading data stored in the plurality of memory blocks based on the history read table. When the read operation fails, a memory controller changes a level of a read voltage, and controls the memory device to perform a read retry operation of retrying the read operation by using the changed read voltage. When the read retry operation passes, the memory controller determines whether the history read table is to be updated by comparing the root bit information of the read retry operation with the root bit information of the history read table.

Abstract: A memory system includes a storage medium including a target memory region having a plurality of memory units; and a controller configured to store data into one or more target memory units, each of which is estimated to take less time to perform a write operation thereon than any of the other memory units among the plurality of memory units, when performing a memory dump operation due to a sudden power off.

Abstract: A method for operating a memory system includes: performing a read operation in response to a first tag; performing a read operation in response to a second tag; performing a defense code operation corresponding to the first tag; performing an error correction code (KC) operation on data output through the defense code operation corresponding to the first tag; and performing a defense code operation corresponding to the second tag, wherein the read operation in response to the second tag is started before the ECC operation corresponding to the first tag is completed, and wherein the defense code operation corresponding to the second tag is performed using a result of the defense code operation corresponding to the first tag.

Abstract: A memory system, a memory controller and an operating method are disclosed. By determining, based on status check delay information, a time point at which a status check command is sent to a memory device and updating the status check delay information while the memory device is in an idle state, it is possible to minimize a degradation in the performance of a program operation for the memory device including a plurality of memory dies, and it is possible to reflect a variation in an operation characteristic of the memory device, on the program operation.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to exemplary embodiments of the present disclosure, the memory system may store information on a number of error bits generated in a first read operation in an error bit history set, when the number of error bits generated in the first read operation for a first memory block among the plurality of memory blocks is greater than or equal to a first io threshold and less than a second threshold, and may repeat, during a read operation performed after the first read operation for the first memory block, an operation of calibrating a history read bias corresponding to the first memory block until a set termination condition is satisfied.

Abstract: A memory controller performs an efficient error correction operation. The memory controller controls a memory device. The memory controller includes: an error corrector configured to perform one or more error correction operations to correct an error included in data read from the memory device during a read operation, the one or more error correction operations including a first error correction operation performed using a first read voltage determined based on a threshold voltage distribution obtained by assuming that a number of memory cells in an erase state is equal to a number of memory cells in a program state and a data controller in communication with the error corrector to receive first error correction data obtained from the first error correction operation and configured to store the first error correction data in the memory controller.

Abstract: An operating method for a data storage device includes providing a nonvolatile memory device including a plurality of pages; segmenting an address map which maps a logical address provided from a host device and a physical address of the nonvolatile memory device, by a plurality of address map segments according to a segment size that is set depending on a quality of service time allowed to process a request of the host device and an unprocessed workload; and flushing at least one of the address map segments in the nonvolatile memory device after processing the unprocessed workload.

Abstract: Embodiments relate to a memory system, a memory controller, and a method of operating the same, wherein a plurality of super memory blocks are set, a parity for data stored in the first super memory block is calculated, the calculated parity is stored in a parity buffer, and the parity stored in the parity buffer is written to one of a plurality of parity blocks included in a memory device. Thus, it is possible to solve the problem that the time for writing data to the memory device is delayed due to the time for calculating the parity, and to efficiently manage the parities stored in the memory device.

Abstract: The present disclosure relates to a memory controller and a method of operating the memory controller. The memory controller controlling a memory device including a plurality of planes includes a central processing unit (CPU) generating a command corresponding to a request from a host, a command queue storing the command, counter logic assigning to the command, number information corresponding to an order in which the command is generated and flag information indicating a level at which an operation corresponding to the command is performed, and a command queue controller controlling the command queue to transfer the command stored in the command queue to one of the plurality of planes corresponding to the command on the basis of the number information and the flag information.

Abstract: A memory controller performs an efficient error correction operation. The memory controller controls a memory device. The memory controller includes: an error corrector configured to perform one or more error correction operations to correct an error included in data read from the memory device during a read operation, the one or more error correction operations including a first error correction operation performed using a first read voltage determined based on a threshold voltage distribution obtained by assuming that a number of memory cells in an erase state is equal to a number of memory cells in a program state and a data controller in communication with the error corrector to receive first error correction data obtained from the first error correction operation and configured to store the first error correction data in the memory controller.

Abstract: A data storage device including a memory device and a memory controller is disclosed. The memory controller including a super block includes a parity controller in communication with a memory device including a plurality of pages and configured to generate a first parity using data to be written to a first group of pages among the plurality of pages, and generate a second parity using data to be written to a second group of pages among the plurality of pages, a write operation controller configured to control the memory device to store the first parity and the second parity, and an error correction circuitry coupled to apply the first parity and the second parity to correct at least one of the plurality of pages arranged to belong to the first group of pages and the second group of pages.

Abstract: A memory controller having improved wear-leveling performance controls a memory device including a plurality of memory blocks. The memory controller includes a read operation controller, a cell state determiner, and a read reclaim controller. The read operation controller controls the memory device to read selected memory cells of a first block among the plurality of memory blocks by using at least one reference voltage. The cell state determiner compares a number of memory cells among the selected memory cells that are read as first memory cell with a reference number corresponding to the at least one reference voltage, and generates cell state information indicating a memory cell degradation degree corresponding to at least one state. The read claim controller controls the memory device to copy data stored in the first block to a second block, based on a comparison between the memory cell degradation degree with a threshold degradation degree.

Abstract: A memory controller having improved read performance controls a memory device including a plurality of memory cells. The memory controller includes a read operation controller, a history bias storage, and a read voltage setting circuit. The read operation controller read data stored selected memory cells among the plurality of memory cells. The history bias storage stores a plurality of history mean biases, which are mean biases of a plurality of threshold voltage distributions that the plurality of memory cells have, and a plurality of reference cell count values respectively corresponding to the plurality of threshold voltage distributions.

Abstract: In a memory controller configured to control a memory device including a plurality of memory blocks, the memory controller comprising: a memory interface configured to exchange data with the memory device; and a pre-program controller configured to perform a read operation on a last page of a program sequence for a plurality of pages in an erase target memory block when the memory device is in an idle state, and perform a pre-program operation on the erase target memory block according to the result obtained by performing the read operation, wherein the erase target memory block is a memory block on which an erase operation is to be performed among the plurality of memory blocks, and wherein the erase operation on the erase target memory block is performed after the pre-program operation is performed.

Abstract: A memory system includes a storage medium including a target memory region having a plurality of memory units; and a controller configured to store data into one or more target memory units, each of which is estimated to take less time to perform a write operation thereon than any of the other memory units among the plurality of memory units, when performing a memory dump operation due to a sudden power off.