Patents by Inventor Min-jan Chen

Min-jan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selective CESL structure for CMOS application
    Patent number: 7696578
    Abstract: A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: April 13, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lin Chen, Min-jan Chen, Jau-Jey Wang
  • Selective CESL structure for CMOS application
    Publication number: 20070181951
    Abstract: A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.
    Type: Application
    Filed: February 8, 2006
    Publication date: August 9, 2007
    Inventors: Chia-Lin Chen, Min-Jan Chen, Jau-Jey Wang