Abstract: A superconducting flux qubit readout system may include an input-output system connected to at least one shift register, the shift register comprising a first set, a second set, and a third set of shift register stages arranged in series, the first set of shift register stages coupled to a first set of qubits by a first plurality of latches, and the second set of shift register stages coupled to a second set of qubits by a second plurality of latches. Reading out states of a first set of qubits may include: shifting qubit state information to first holding latches communicatively coupled to a shift register; obtaining, by each shift register stage of the first set of shift register stages, state information from the first holding latches; and, propagating information along the shift register.

Abstract: Systems and methods for capacitance tuning of devices in quantum processors are described. One implementation is a quantum processor with a first current path having a first loop, a Josephson structure with at least one Josephson junction interrupting the first loop, a second current path connected to the first current path, and a flux bias. The second current path has a first node spaced from a second node, a capacitor separating the first node and the second node, and a voltage gain tuner, the voltage gain tuner being inductively coupled to the inductance of the first current path. The flux bias is coupled to the voltage gain tuner and controls the voltage gain tuner to vary a voltage ratio between the first node and the second node, thereby influencing the capacitance of the first current path.

Abstract: Programmable components of a quantum processor may be selectively programmed using digital to analog converters (DACs). A DAC with a first stage and a second stage and first and second quantum flux parametron (OFF) loops galvanically coupled to and extending from a respective one of the first stage and the second stage is discussed. The first stage has a first storage loop interrupted by a first Josephson junction and an interface for communicating with an external component. The second stage has a second storage loop interrupted by a second Josephson junction, the second storage loop galvanically coupled to the first storage loop, the first Josephson junction and the second Josephson junction coupled in series to a first control line. A method of loading flux quanta into targeted DAC stages is also discussed.