Abstract: A CMOS light sensor and the operation method thereof are disclosed. The CMOS light sensor has a plurality of light sensing lines and a plurality of capacitor lines. Each light sensing line has a plurality of light sensors such that the number of capacitors in each capacitor line is smaller than the number of light sensing cells in each light sensing line. The capacitors are used for holding a portion of the potentials produced by the light sensing cells due to illumination. The method of operating the CMOS light sensor includes transferring the data captured by the light sensing line to the capacitor line and reading out the data according to a pre-defined order so that the leakage of charges from the capacitor is reduced.

Abstract: A CMOS light sensor and the operation method thereof are disclosed. The CMOS light sensor has a plurality of light sensing lines and a plurality of capacitor lines. Each light sensing line has a plurality of light sensors such that the number of capacitors in each capacitor line is smaller than the number of light sensing cells in each light sensing line. The capacitors are used for holding a portion of the potentials produced by the light sensing cells due to illumination. The method of operating the CMOS light sensor includes transferring the data captured by the light sensing line to the capacitor line and reading out the data according to a pre-defined order so that the leakage of charges from the capacitor is reduced.

Abstract: A CMOS light sensor and the operation method thereof are disclosed. The CMOS light sensor has a plurality of light sensing lines and a plurality of capacitor lines. Each light sensing line has a plurality of light sensors such that the number of capacitors in each capacitor line is smaller than the number of light sensing cells in each light sensing line. The capacitors are used for holding a portion of the potentials produced by the light sensing cells due to illumination. The method of operating the CMOS light sensor includes transferring the data captured by the light sensing line to the capacitor line and reading out the data according to a pre-defined order so that the leakage of charges from the capacitor is reduced.

Abstract: A semiconductor package positioned on a first substrate includes a second substrate having a first surface and a second surface, a chip positioned on the first surface of the second substrate, a plurality of first bonding balls positioned on the second surface of the second substrate and arranged in a line along a first direction for connecting the second substrate to the first substrate, and at least a dummy bonding bar positioned on the second surface of the second substrate for connecting the second substrate to the first substrate and preventing the semiconductor package from inclining to one side.

Abstract: A CMOS light sensor and the operation method thereof are disclosed. The CMOS light sensor has a plurality of light sensing lines and a plurality of capacitor lines. Each light sensing line has a plurality of light sensors such that the number of capacitors in each capacitor line is smaller than the number of light sensing cells in each light sensing line. The capacitors are used for holding a portion of the potentials produced by the light sensing cells due to illumination. The method of operating the CMOS light sensor includes transferring the data captured by the light sensing line to the capacitor line and reading out the data according to a pre-defined order so that the leakage of charges from the capacitor is reduced.

Abstract: A method of forming a semiconductor device having reduced interconnect-line parasitic capacitance is provided. The method includes the following steps. First, a substrate is provided and a plurality of interconnect lines are formed on the substrate. A barrier layer is then formed. Next, the barrier layer is hardened and thinned so as to make the barrier layer having a thin-film attribute. Following that, a separation layer is formed by filling the space between and above the interconnect lines with a dielectric. Then, the dielectric is foamed. After that, an insulating layer is formed. Finally, the dielectric is condensed such that air gaps are formed in the separation layer.

Abstract: A method of forming a semiconductor device having reduced interconnect-line parasitic capacitance is provided. The method includes the following steps. First, a substrate is provided and a plurality of interconnect lines are formed on the substrate. A barrier layer is then formed. Next, the barrier layer is hardened and thinned so as to make the barrier layer having a thin-film attribute. Following that, a separation layer is formed by filling the space between and above the interconnect lines with a dielectric. Then, the dielectric is foamed. After that, an insulating layer is formed. Finally, the dielectric is condensed such that air gaps are formed in the separation layer.