Abstract: Disclosed are a BIPV-applicable high-power shingled photovoltaic module and a manufacturing method therefor, the module comprising: a solar panel having a shingled array structure; a first sealant stacked on the solar panel so as to protect the solar panel; a second sealant stacked under the solar panel in order to protect the solar panel; a front cover through which the sunlight passes, and which is stacked on the first sealant so as to protect the first sealant; and a first back sheet stacked under the second sealant in order to protect the solar panel from the outside environment, and thus aesthetic impression and reflectance reduction of a high-power shingled photovoltaic module are increased so that use as an external design element of a building is possible.

Abstract: Disclosed are a high-power shingled photovoltaic string controllable in length and width and a method for manufacturing a module thereof. The method for manufacturing a high-power shingled photovoltaic module comprises the steps of: primarily cutting a bulk silicon substrate along a first cut line parallel to a bus bar electrode using laser scribing, thereby dividing the bulk silicon substrate into unit cells; forming an intermediate processing junction substrate by shingled-joining a plurality of unit cells according to the length of a string; forming the string by secondarily cutting the intermediate processing junction substrate seated on a substrate fixing jig, the intermediate processing junction substrate being cut along a second cut line that is perpendicular to the bus bas electrode and set according to the width of the string; and laminating a protective member on the surfaces of a plurality of strings to form a photovoltaic module.

Abstract: The disclosed invention provides a photovoltaic module with an improved electrode structure of a solar cell and having any of various shapes. The photovoltaic module includes electrode members each including a finger electrode and a busbar electrode on a front surface of a solar cell to correspond to the number of divided cells, wherein the finger electrode is disposed as a plurality of finger electrodes in a first direction parallel to a short side of a divided unit cell, and the busbar electrode includes a collection electrode line which extends in a second direction parallel to a long side of the divided unit cell and connects ends of the plurality of finger electrodes and a connecting electrode line which is branched off from an end of the collection electrode line and extends in the first direction to be electrically connected to another unit cell.

Abstract: A method of controlling a semiconductor process includes performing a semiconductor process using plasma in a chamber including an electrostatic chuck (ESC) on which a wafer is seated, obtaining an ESC voltage supplied to the ESC, an ESC current detected from the ESC, and bias power supplied to a bias electrode in the chamber, while the semiconductor process is being performed in the chamber, and determining whether a discharge has occurred between the ESC and the wafer using at least one of the ESC voltage, the ESC current, and the bias power.

Abstract: A plasma processing apparatus can include a process chamber and a susceptor in a lower portion of the process chamber. A chuck can be on the susceptor, where the chuck can include an upper surface configured to mount a wafer thereon. A shower head can include a plurality of first regions including gas ports and including a plurality of gas supply pipes separately communicating with the first regions and configured to independently supply a process gas into the process chamber toward the upper surface of the chuck, where each of the gas ports in the first regions includes a plurality of sub-gas ports. A process gas supplier can be configured to supply the process gas to the gas supply pipes and a control unit configured to independently control amounts of the process gas supplied to the gas supply pipes.

Abstract: A method of controlling a semiconductor process includes performing a semiconductor process using plasma in a chamber including an electrostatic chuck (ESC) on which a wafer is seated, obtaining an ESC voltage supplied to the ESC, an ESC current detected from the ESC, and bias power supplied to a bias electrode in the chamber, while the semiconductor process is being performed in the chamber, and determining whether a discharge has occurred between the ESC and the wafer using at least one of the ESC voltage, the ESC current, and the bias power.

Abstract: Disclosed are a plasma etching apparatus and a method of manufacturing semiconductor devices using the same. The plasma etching apparatus includes a process chamber. A source supplier is positioned at an upper portion of the process chamber. The source supplier is configured to supply source gases for an etching process. A substrate holder is positioned at a lower portion of the process chamber opposite to the source supplier. The substrate holder is configured to support a substrate. A first power source is configured to apply a high frequency power to capacitively couple the source gases into a capacitively coupled plasma (CCP) in the process chamber. A second power source is configured to apply a low frequency pulse power at a low duty ratio of less than or equal to about 0.5:1. The low frequency pulse power is configured to guide the CCP toward the substrate supported by the substrate holder.

Abstract: A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer. The hardmask pattern has a first opening, and the bowing control pattern has a second opening. A third opening passes through the intermediate layer and is connected to the second opening. The bowing control pattern includes first and second edges on a lower end of the second opening, and a third edge on an upper end of the second opening. When a first point on the first edge, a second point on the second edge, and a third point on a horizontal line passing through the third edge are defined, an intersecting angle between a first side from the first point to the second point, and a second side from the second point to the third point is from about 50° to about 80°.

Abstract: In a method forming patterns, a layer on a substrate is patterned by a first etching process using an etch mask to form a plurality of first preliminary patterns and a plurality of second preliminary patterns. The second preliminary patterns are spaced apart from each other at a second distance larger than a first distance at which the first preliminary patterns are spaced apart. First and second coating layers are formed on sidewalls of the first and second preliminary patterns, respectively, and the first and second coating layers and portions of the first and second preliminary patterns are removed by a second etching process using the etch mask to form a plurality of first patterns and a plurality of second patterns. The first patterns have widths that are smaller than widths of the first preliminary patterns. The first patterns may have generally vertical sidewalls relative to the substrate.

Abstract: A method of fabricating a semiconductor device is provided and includes forming one or more molding layers on a substrate, forming a silicon mask layer, first and second mask layers, and a mask pattern having a different etch selectivity to be vertically aligned on the molding layer, patterning the second mask layer with a second mask pattern using the mask pattern as an etching mask, patterning the first mask layer with a first mask pattern using the second mask pattern as an etching mask, patterning the silicon mask layer with a silicon mask pattern using the first mask pattern as an etching mask, changing the silicon mask pattern to a hard mask pattern having an improved etch selectivity by doping impurities into the silicon mask pattern, forming a hole having a high aspect ratio contact (HARC) structure vertically passing through the molding layer using the hard mask pattern as an etching mask, and removing the hard mask pattern.

Abstract: A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer. The hardmask pattern has a first opening, and the bowing control pattern has a second opening. A third opening passes through the intermediate layer and is connected to the second opening. The bowing control pattern includes first and second edges on a lower end of the second opening, and a third edge on an upper end of the second opening. When a first point on the first edge, a second point on the second edge, and a third point on a horizontal line passing through the third edge are defined, an intersecting angle between a first side from the first point to the second point, and a second side from the second point to the third point is from about 50° to about 80°.

Abstract: A plasma dry etching apparatus includes a pedestal in a process chamber, the pedestal being configured to support a wafer, a cathode electrode and a plate electrode in the process chamber, the cathode and plate electrodes being configured to apply radio-frequency (RF) power, an edge ring on an edge of the pedestal, a coupling ring having a first side on the pedestal and a second side on the edge ring, an edge cooling unit in the coupling ring, the edge cooling unit being configured to cool the edge ring to drop a temperature of an extreme edge of the wafer, and an edge heating unit in the coupling ring, the edge heating unit being configured to heat the edge ring to raise the temperature of an extreme edge of the wafer.

Abstract: Method of forming fine patterns and methods of fabricating semiconductor devices by which a photoresist (PR) pattern may be transferred to a medium material layer with a small thickness and a high etch selectivity with respect to a hard mask to form a medium pattern and the hard mask may be formed using the medium pattern. According to the methods, the PR pattern may have a low aspect ratio so that a pattern can be transferred using a PR layer with a small thickness without collapsing the PR pattern.

Abstract: Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.

Abstract: Method of forming fine patterns and methods of fabricating semiconductor devices by which a photoresist (PR) pattern may be transferred to a medium material layer with a small thickness and a high etch selectivity with respect to a hard mask to form a medium pattern and the hard mask may be formed using the medium pattern. According to the methods, the PR pattern may have a low aspect ratio so that a pattern can be transferred using a PR layer with a small thickness without collapsing the PR pattern.

Abstract: In a method forming patterns, a layer on a substrate is patterned by a first etching process using an etch mask to form a plurality of first preliminary patterns and a plurality of second preliminary patterns. The second preliminary patterns are spaced apart from each other at a second distance larger than a first distance at which the first preliminary patterns are spaced apart. First and second coating layers are formed on sidewalls of the first and second preliminary patterns, respectively, and the first and second coating layers and portions of the first and second preliminary patterns are removed by a second etching process using the etch mask to form a plurality of first patterns and a plurality of second patterns. The first patterns have widths that are smaller than widths of the first preliminary patterns. The first patterns may have generally vertical sidewalls relative to the substrate.

Abstract: A plasma dry etching apparatus includes a pedestal in a process chamber, the pedestal being configured to support a wafer, a cathode electrode and a plate electrode in the process chamber, the cathode and plate electrodes being configured to apply radio-frequency (RF) power, an edge ring on an edge of the pedestal, a coupling ring having a first side on the pedestal and a second side on the edge ring, an edge cooling unit in the coupling ring, the edge cooling unit being configured to cool the edge ring to drop a temperature of an extreme edge of the wafer, and an edge heating unit in the coupling ring, the edge heating unit being configured to heat the edge ring to raise the temperature of an extreme edge of the wafer.

Abstract: Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.

Abstract: A plasma processing apparatus using a capacitive coupled plasma (CCP) source requiring a low pressure range of about 25 mT or less and a method thereof are disclosed. Plasma source power may be applied in a pulse mode to either one of upper and lower electrodes in a chamber, which generates plasma and processes a semiconductor substrate, and plasma maintaining power may be continuously applied to the other of the upper and lower electrodes, such that a stable pulse plasma process may be performed in a low pressure range of about 25 mT or less.

Abstract: Provided herein are methods of forming a metal oxide layer pattern on a substrate including providing a preliminary metal oxide layer on a substrate; etching the preliminary metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increases in a vertically downward direction; and etching the preliminary metal oxide layer pattern to form a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer.