Patents by Inventor Min Keen Tang

Min Keen Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11189574
    Abstract: A microelectronic package may be fabricated with a microelectronic substrate, a microelectronic die electrically attached to the microelectronic substrate, and an electromagnetic interference shield layer contacting one or both of the microelectronic substrate and the microelectronic die, wherein the electromagnetic interference shield layer has an electrical conductivity between about 10,000 siemens per meter and 100,000 siemens per meter. The specific range of electrical conductivity results in electromagnetic fields either generated by the microelectronic die or generated by components external to the microelectronic package scattering within the electromagnetic interference shield layer and attenuating. Thus, the electromagnetic interference shield layer can prevent electromagnetic field interference without the need to be grounded.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Li-Sheng Weng, Chung-Hao Chen, James C. Matayabas, Jr., Min Keen Tang
  • Publication number: 20210118809
    Abstract: A microelectronic package may be fabricated with a microelectronic substrate, a microelectronic die electrically attached to the microelectronic substrate, and an electromagnetic interference shield layer contacting one or both of the microelectronic substrate and the microelectronic die, wherein the electromagnetic interference shield layer has an electrical conductivity between about 10,000 siemens per meter and 100,000 siemens per meter. The specific range of electrical conductivity results in electromagnetic fields either generated by the microelectronic die or generated by components external to the microelectronic package scattering within the electromagnetic interference shield layer and attenuating. Thus, the electromagnetic interference shield layer can prevent electromagnetic field interference without the need to be grounded.
    Type: Application
    Filed: May 31, 2017
    Publication date: April 22, 2021
    Applicant: Intel Corporation
    Inventors: Li-Sheng Weng, Chung-Hao Chen, James C. Matayabas, Jr., Min Keen Tang
  • Patent number: 10522898
    Abstract: Generally, this disclosure provides systems, devices and methods for integration of millimeter wave antennas in platforms with reduced form factors while maintaining or improving antenna gain. An antenna assembly may include a first planar substrate; a ground plane disposed on the first planar substrate; a second planar substrate disposed on the ground plane; and an antenna radiation element disposed on the second planar substrate. The antenna radiation element may be configured to transmit a signal in the millimeter wave frequency region. The assembly may also include a via to provide a conductive path for the signal from a microstrip feed line, beneath the first planar substrate, to the antenna radiation element. The assembly may further include a dielectric layer disposed on the antenna radiation element to provide increased antenna gain under conditions of reduced air gap between the antenna radiation element and a structural element of an enclosing platform.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: December 31, 2019
    Assignee: INTEL CORPORATION
    Inventors: Min Keen Tang, Ana M. Yepes, Yaniv Michaeli, Menashe Soffer
  • Publication number: 20190058240
    Abstract: Generally, this disclosure provides systems, devices and methods for integration of millimeter wave antennas in platforms with reduced form factors while maintaining or improving antenna gain. An antenna assembly may include a first planar substrate; a ground plane disposed on the first planar substrate; a second planar substrate disposed on the ground plane; and an antenna radiation element disposed on the second planar substrate. The antenna radiation element may be configured to transmit a signal in the millimeter wave frequency region. The assembly may also include a via to provide a conductive path for the signal from a microstrip feed line, beneath the first planar substrate, to the antenna radiation element. The assembly may further include a dielectric layer disposed on the antenna radiation element to provide increased antenna gain under conditions of reduced air gap between the antenna radiation element and a structural element of an enclosing platform.
    Type: Application
    Filed: August 30, 2016
    Publication date: February 21, 2019
    Inventors: MIN KEEN TANG, ANA M. YEPES, YANIV MICHAELI, MENASHE SOFFER
  • Patent number: 9900976
    Abstract: Apparatus and method to provide integrated circuit (IC) package integrity without adverse performance degradation are disclosed herein. In some embodiments, an apparatus may include one or more integrated circuits (ICs); a metallic structure that encircles the one or more ICs without being in contact with the one or more ICs, wherein the metallic structure is without an electrical ground; and a conductive epoxy layer disposed below and in contact with the metallic structure, wherein the conductive epoxy is to reduce an electromagnetic field induced by the metallic structure in response to a presence of a wireless signal that operates at approximately a resonant frequency associated with the metallic structure.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventors: Chung-Hao Chen, Min Keen Tang, Li-Sheng Weng
  • Patent number: 9893444
    Abstract: A board-edge interconnection module features integrated capacitive coupling, which enables a board design employing the module to avoid having AC capacitors and flexible cables with bulky connectors. The recovered real estate enables further miniaturization, enabling the component to be used on a wide variety of devices, including ultra-mobile computing devices.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Eng Huat Goh, Bok Eng Cheah, Su Sin Florence Phun, Khang Choong Yong, Min Keen Tang
  • Publication number: 20170093064
    Abstract: A board-edge interconnection module features integrated capacitive coupling, which enables a board design employing the module to avoid having AC capacitors and flexible cables with bulky connectors. The recovered real estate enables further miniaturization, enabling the component to be used on a wide variety of devices, including ultra-mobile computing devices.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 30, 2017
    Inventors: JACKSON CHUNG PENG KONG, ENG HUAT GOH, BOK ENG CHEAH, SU SIN FLORENCE PHUN, KHANG CHOONG YONG, MIN KEEN TANG
  • Publication number: 20160380386
    Abstract: In one example an electronic device comprises a housing, a receptacle in the housing comprising an opening at a distal end to receive a plug, a data connector positioned in the receptacle to provide a communication connection, and an electrostatic conductor assembly positioned proximate the opening in the receptacle, wherein the electrostatic conductor assembly comprises a dedicated discharge path and a conductive pin mounted on a retention latch and moveable between a first position in which the conductive pin is in electrical contact with the data connector and a second position in which the conductive pin is not in electrical contact with the data connector. Other examples may be described.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Applicant: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Kuan-Yu Chen, Bok Eng Cheah, Boon Ping Koh, Min Keen Tang, Howard L. Heck, Kooi Chi Ooi
  • Publication number: 20160211619
    Abstract: In one example an electronic device comprises a housing. A receptacle in the housing comprising an opening at a distal end to receive a plug and an electrostatic conductor assembly positioned proximate the opening in the receptacle, wherein the electrostatic conductor assembly is coupled to a dedicated electrical discharge path. Other examples may be described.
    Type: Application
    Filed: January 21, 2015
    Publication date: July 21, 2016
    Applicant: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Howard L Heck, Kuan-Yu Chen, Boon Ping Koh, Min Keen Tang, Kooi Chi Ooi