Patents by Inventor Min Kuck Cho

Min Kuck Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10985074
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 20, 2021
    Assignee: Key Foundry Co., Ltd
    Inventors: Min Kuck Cho, Myeong Seok Kim, In Chul Jung
  • Publication number: 20210028183
    Abstract: A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.
    Type: Application
    Filed: February 26, 2020
    Publication date: January 28, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Kwang Il KIM, Yang Beom KANG, Jung Hwan LEE, Min Kuck CHO, Hyun Chul KIM
  • Publication number: 20210005622
    Abstract: A nonvolatile memory device includes a cell array formed on a substrate, and a control gate pickup structure, wherein the cell array comprises floating gates, and a control gate surrounding the floating gates, wherein the control gate pickup structure comprises a floating gate polysilicon layer, a control gate polysilicon layer surrounding the floating gate polysilicon layer and connected to the control gate, and at least one contact plug formed on the control gate polysilicon layer.
    Type: Application
    Filed: January 7, 2020
    Publication date: January 7, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Min Kuck CHO, Seung Hoon LEE
  • Patent number: 10453755
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 22, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Min Kuck Cho, Myeong Seok Kim, In Chul Jung
  • Publication number: 20190198401
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Application
    Filed: January 25, 2019
    Publication date: June 27, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Min Kuck CHO, Myeong Seok KIM, In Chul JUNG
  • Publication number: 20180350696
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 6, 2018
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Min Kuck CHO, Myeong Seok KIM, In Chul JUNG
  • Patent number: 10062616
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: August 28, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Min Kuck Cho, Myeong Seok Kim, In Chul Jung
  • Publication number: 20180025948
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Application
    Filed: December 23, 2016
    Publication date: January 25, 2018
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Min Kuck CHO, Myeong Seok KIM, In Chul JUNG
  • Patent number: 7553724
    Abstract: The present invention relates to a method manufacturing a code address memory (CAM) cell. The present invention uses a dielectric film in which an oxide film and a nitride film between a floating gate and a control gate in a flash memory cell are stacked as a gate insulating film between a semiconductor substrate and a gate in the CAM cell. Therefore, the present invention can reduce the area of a peripheral circuit region and stably secure repaired data since the CAM cell can be stably driven at a low operating voltage and additional boosting circuit is thus not required.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: June 30, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jum Soo Kim, Sung Mun Jung, Min Kuck Cho, Young Bok Lee
  • Publication number: 20030203574
    Abstract: The present invention relates to a method of manufacturing a nonvolatile memory cell. The present invention uses tungsten (W) as an upper layer of a control gate electrode in order to integrate the memory cell and performs an ion implantation process for forming a source region and a drain region before a selective oxidization process that is performed to prevent abnormal oxidization of tungsten (W). Therefore, the present invention can reduce a RC delay time of word lines depending on integration of the memory cell and also secure a given distance between a silicon substrate and a tunnel oxide film. As a result, the present invention can solve a data retention problem of the flash memory.
    Type: Application
    Filed: May 28, 2003
    Publication date: October 30, 2003
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Jum Soo Kim, Sung Mun Jung, Sang Bum Lee, Min Kuck Cho, Young Bok Lee
  • Patent number: 6620684
    Abstract: The present invention relates to a method of manufacturing a nonvolatile memory cell. The present invention uses tungsten (W) as an upper layer of a control gate electrode in order to integrate the memory cell and performs an ion implantation process for forming a source region and a drain region before a selective oxidization process that is performed to prevent abnormal oxidization of tungsten (W). Therefore, the present invention can reduce a RC delay time of word lines depending on integration of the memory cell and also secure a given distance between a silicon substrate and a tunnel oxide film. As a result, the present invention can solve a data retention problem of the flash memory.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: September 16, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jum Soo Kim, Sung Mun Jung, Sang Bum Lee, Min Kuck Cho, Young Bok Lee
  • Publication number: 20030003657
    Abstract: The present invention relates to a method of manufacturing a nonvolatile memory cell. The present invention uses tungsten (W) as an upper layer of a control gate electrode in order to integrate the memory cell and performs an ion implantation process for forming a source region and a drain region before a selective oxidization process that is performed to prevent abnormal oxidization of tungsten (W). Therefore, the present invention can reduce a RC delay time of word lines depending on integration of the memory cell and also secure a given distance between a silicon substrate and a tunnel oxide film. As a result, the present invention can solve a data retention problem of the flash memory.
    Type: Application
    Filed: December 28, 2001
    Publication date: January 2, 2003
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jum Soo Kim, Sung Mun Jung, Sang Bum Lee, Min Kuck Cho, Young Bok Lee
  • Publication number: 20020197777
    Abstract: The present invention relates to a method manufacturing a code address memory (CAM) cell. The present invention uses a dielectric film in which an oxide film and a nitride film between a floating gate and a control gate in a flash memory cell are stacked as a gate insulating film between a semiconductor substrate and a gate in the CAM cell. Therefore, the present invention can reduce the area of a peripheral circuit region and stably secure repaired data since the CAM cell can be stably driven at a low operating voltage and additional boosting circuit is thus not required.
    Type: Application
    Filed: December 28, 2001
    Publication date: December 26, 2002
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jum Soo Kim, Sung Mun Jung, Min Kuck Cho, Young Bok Lee
  • Patent number: 5888869
    Abstract: The present invention discloses a method of fabricating a flash memory device. In the present invention, since the dielectric film formed in the memory cell region is only exposed to the cleaning solution which is used in cleaning process preformed after removing the dielectric film formed in the low voltage transistor region, the number of damages applied to the dielectric film can be minimized, therefore, a good dielectric film can be obtained.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: March 30, 1999
    Assignee: Hyundai Electronics Industries, Co., Ltd.
    Inventors: Min Kuck Cho, Jong Oh Kim