Patents by Inventor Min Kuck Cho

Min Kuck Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250056863
    Abstract: A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate
    Type: Application
    Filed: October 31, 2024
    Publication date: February 13, 2025
    Applicant: SK keyfoundry Inc.
    Inventors: Min Kuck CHO, Jae Hoon KIM, Seung Hoon LEE
  • Patent number: 12176402
    Abstract: A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: December 24, 2024
    Assignee: SK keyfoundry Inc.
    Inventors: Min Kuck Cho, Jae Hoon Kim, Seung Hoon Lee
  • Patent number: 11991878
    Abstract: A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: May 21, 2024
    Assignee: SK keyfoundry Inc.
    Inventors: Kwang Il Kim, Yang Beom Kang, Jung Hwan Lee, Min Kuck Cho, Hyun Chul Kim
  • Publication number: 20240049463
    Abstract: A single poly non-volatile memory device is provided. The single poly non-volatile memory device is formed in a semiconductor substrate, and includes a sensing transistor, a selection transistor, and a capacitor, wherein a thickness of a selection gate insulating film is formed to be thicker than a thickness of a sensing gate insulating film, wherein a thickness of a control gate insulating film of the capacitor is formed to be the same, or greater than, a thickness of the sensing gate insulating film, and wherein the sensing gate of the sensing transistor and the control gate of the capacitor are physically and electrically connected to each other.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 8, 2024
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Su Jin KIM, Min Kuck CHO, Jung Hwan LEE, In Chul JUNG
  • Publication number: 20230378284
    Abstract: A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate
    Type: Application
    Filed: July 27, 2023
    Publication date: November 23, 2023
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Min Kuck CHO, Jae Hoon KIM, Seung Hoon LEE
  • Patent number: 11825650
    Abstract: A single poly non-volatile memory device is provided. The single poly non-volatile memory device is formed in a semiconductor substrate, and includes a sensing transistor, a selection transistor, and a capacitor, wherein a thickness of a selection gate insulating film is formed to be thicker than a thickness of a sensing gate insulating film, wherein a thickness of a control gate insulating film of the capacitor is formed to be the same, or greater than, a thickness of the sensing gate insulating film, and wherein the sensing gate of the sensing transistor and the control gate of the capacitor are physically and electrically connected to each other.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: November 21, 2023
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Su Jin Kim, Min Kuck Cho, Jung Hwan Lee, In Chul Jung
  • Publication number: 20230317777
    Abstract: A semiconductor device is provided. The semiconductor device includes a first region having a first gate structure disposed on a substrate and a second region having a second gate structure disposed on the substrate, a hard mask formed on the substrate, the first gate structure, and the second gate structure, a deep trench formed in the substrate between the first region and the second region, and formed to penetrate the hard mask to reach an inside of the substrate, and a planarized gap-fill insulating layer formed on the second gate structure and formed inside the deep trench. A topmost surface of the planarized gap-fill insulating layer and a topmost surface of the hard mask are coplanar.
    Type: Application
    Filed: February 22, 2023
    Publication date: October 5, 2023
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Kwang Il KIM, Min Kuck CHO, Jung Hwan LEE, Yang Beom KANG, Hyun Chul KIM
  • Patent number: 11757011
    Abstract: A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: September 12, 2023
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Min Kuck Cho, Jae Hoon Kim, Seung Hoon Lee
  • Publication number: 20230247830
    Abstract: A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.
    Type: Application
    Filed: April 12, 2023
    Publication date: August 3, 2023
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Kwang Il KIM, Yang Beom KANG, Jung Hwan LEE, Min Kuck CHO, Hyun Chul KIM
  • Patent number: 11696440
    Abstract: A nonvolatile memory device includes a cell array formed on a substrate, and a control gate pickup structure, wherein the cell array comprises floating gates, and a control gate surrounding the floating gates, wherein the control gate pickup structure comprises a floating gate polysilicon layer, a control gate polysilicon layer surrounding the floating gate polysilicon layer and connected to the control gate, and at least one contact plug formed on the control gate polysilicon layer.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: July 4, 2023
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Min Kuck Cho, Seung Hoon Lee
  • Patent number: 11665896
    Abstract: A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: May 30, 2023
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Kwang Il Kim, Yang Beom Kang, Jung Hwan Lee, Min Kuck Cho, Hyun Chul Kim
  • Publication number: 20230059628
    Abstract: A semiconductor device includes: a logic region and a non-volatile memory (NVM) region; a logic gate insulating film disposed on a substrate in the logic region; at least one gate oxidation acceleration ion implantation layer disposed in the NVM region; at least one NVM gate insulating film disposed on the at least one gate oxidation acceleration ion implantation layer; a logic gate electrode disposed on the logic gate insulating film; and at least one NVM gate electrode disposed on the at least one NVM gate insulating film, wherein a thickness of the at least one NVM gate insulating film is equal or greater than a thickness of the logic gate insulating film.
    Type: Application
    Filed: May 13, 2022
    Publication date: February 23, 2023
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Su Jin KIM, Min Kuck CHO, Jung Hwan LEE, In Chul JUNG
  • Publication number: 20230053444
    Abstract: A single poly non-volatile memory device is provided. The single poly non-volatile memory device is formed in a semiconductor substrate, and includes a sensing transistor, a selection transistor, and a capacitor, wherein a thickness of a selection gate insulating film is formed to be thicker than a thickness of a sensing gate insulating film, wherein a thickness of a control gate insulating film of the capacitor is formed to be the same, or greater than, a thickness of the sensing gate insulating film, and wherein the sensing gate of the sensing transistor and the control gate of the capacitor are physically and electrically connected to each other.
    Type: Application
    Filed: December 29, 2021
    Publication date: February 23, 2023
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Su Jin KIM, Min Kuck CHO, Jung Hwan LEE, In Chul JUNG
  • Publication number: 20220359674
    Abstract: A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate
    Type: Application
    Filed: November 18, 2021
    Publication date: November 10, 2022
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Min Kuck CHO, Jae Hoon KIM, Seung Hoon LEE
  • Publication number: 20220246627
    Abstract: A nonvolatile memory device includes a cell array formed on a substrate, and a control gate pickup structure, wherein the cell array comprises floating gates, and a control gate surrounding the floating gates, wherein the control gate pickup structure comprises a floating gate polysilicon layer, a control gate polysilicon layer surrounding the floating gate polysilicon layer and connected to the control gate, and at least one contact plug formed on the control gate polysilicon layer.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 4, 2022
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Min Kuck CHO, Seung Hoon LEE
  • Patent number: 11348931
    Abstract: A nonvolatile memory device includes a cell array formed on a substrate, and a control gate pickup structure, wherein the cell array comprises floating gates, and a control gate surrounding the floating gates, wherein the control gate pickup structure comprises a floating gate polysilicon layer, a control gate polysilicon layer surrounding the floating gate polysilicon layer and connected to the control gate, and at least one contact plug formed on the control gate polysilicon layer.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: May 31, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Min Kuck Cho, Seung Hoon Lee
  • Publication number: 20220157840
    Abstract: A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.
    Type: Application
    Filed: February 7, 2022
    Publication date: May 19, 2022
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Kwang Il KIM, Yang Beom KANG, Jung Hwan LEE, Min Kuck CHO, Hyun Chul KIM
  • Patent number: 11289498
    Abstract: A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: March 29, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Kwang Il Kim, Yang Beom Kang, Jung Hwan Lee, Min Kuck Cho, Hyun Chul Kim
  • Patent number: 10985074
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 20, 2021
    Assignee: Key Foundry Co., Ltd
    Inventors: Min Kuck Cho, Myeong Seok Kim, In Chul Jung
  • Publication number: 20210028183
    Abstract: A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.
    Type: Application
    Filed: February 26, 2020
    Publication date: January 28, 2021
    Applicant: KEY FOUNDRY CO., LTD.
    Inventors: Kwang Il KIM, Yang Beom KANG, Jung Hwan LEE, Min Kuck CHO, Hyun Chul KIM