Abstract: A stacked IC package includes a first die including a first power transmission region, an adapter die stacked on the first die, a second die stacked on the adapter die and including a second power transmission region, and a first power transmission path electrically connected between the second power transmission region and the first power transmission region through the adapter die. The first power transmission path includes a first power transmission part penetrating a portion of the adapter die in a vertical direction from the first power transmission region, a second power transmission part including a connected part in a horizontal direction from the first power transmission part in the adapter die, and a third power transmission part connected to the second power transmission region in the vertical direction from the second power transmission part. A voltage conversion circuit is arranged on the first power transmission path.

Abstract: A display device includes a level shifter and a gate driving circuit that can reduce differences in characteristics among gate signals to improve image quality by controlling a signal waveform of a first clock signal of the m number of clock signals different from a signal waveform of an m-th clock signal when m number of gate signals is output by using m number of clock signals.

Abstract: Disclosed are a gate driver circuit having a reduced size, and a display device including the same. The gate driver circuit includes a plurality of stage circuits. Each stage circuit supplies a gate signal to each of gate lines arranged in a display panel, and includes a M node, a Q node, a QH node, and a QB node. Each stage circuit includes a gate signal output module configured to operate based on a voltage level of the Q node or a voltage level of the QB node to output first to j-th gate signals based on first to j-th scan clock signals or a first low-potential voltage.

Abstract: A gate driver circuit includes a plurality of stage circuits, each stage circuit supplies a gate signal to each of gate lines arranged in a display panel and includes a M node, a Q node, a QH node, and a QB node, and each stage circuit includes a line selector, a Q node controller, a Q node and QH node stabilizer, an inverter, a QB node stabilizer, a carry signal output module, and a gate signal output module, and a high voltage level period of a carry clock signal is set not to overlap with a high voltage level period of a first scan clock signal.

Abstract: Disclosed are a gate driver circuit having a reduced size, and a display device including the same. The gate driver circuit includes a plurality of stage circuits. Each stage circuit supplies a gate signal to each of gate lines arranged in a display panel, and includes a M node, a Q node, a QH node, and a QB node. Each stage circuit includes a gate signal output module configured to operate based on a voltage level of the Q node or a voltage level of the QB node to output first to j-th gate signals based on first to j-th scan clock signals or a first low-potential voltage.

Abstract: A display device includes a level shifter and a gate driving circuit that can reduce differences in characteristics among gate signals to improve image quality by controlling a signal waveform of a first clock signal of the m number of clock signals different from a signal waveform of an m-th clock signal when m number of gate signals is output by using m number of clock signals.

Abstract: A gate driver circuit includes a plurality of stage circuits, each stage circuit supplies a gate signal to each of gate lines arranged in a display panel and includes a M node, a Q node, a QH node, and a QB node, and each stage circuit includes a line selector, a Q node controller, a Q node and QH node stabilizer, an inverter, a QB node stabilizer, a carry signal output module, and a gate signal output module, and a high voltage level period of a carry clock signal is set not to overlap with a high voltage level period of a first scan clock signal.

Abstract: A gate driver has a plurality of stages for outputting a gate signal for image at a time of display driving and outputting a gate signal for sensing at a time of sensing driving that follows the display driving. Each of the stages includes a pixel line selecting unit charging an M node with a first preceding stage carry signal according to a pixel line selection signal of a gate-on voltage during the display driving and charging a Q node with a first high-potential power supply voltage according to a sensing start signal of a gate-on voltage and a charged voltage of the M node during the sensing driving, and an output unit outputting a scan clock of a gate-on voltage as the gate signal for sensing while the Q node maintains a charged state on the sensing driving, wherein the first high-potential power supply voltage is higher at the time of the sensing driving than at the time of the display driving.

Abstract: A gate driver has a plurality of stages for outputting a gate signal for image at a time of display driving and outputting a gate signal for sensing at a time of sensing driving that follows the display driving. Each of the stages includes a pixel line selecting unit charging an M node with a first preceding stage carry signal according to a pixel line selection signal of a gate-on voltage during the display driving and charging a Q node with a first high-potential power supply voltage according to a sensing start signal of a gate-on voltage and a charged voltage of the M node during the sensing driving, and an output unit outputting a scan clock of a gate-on voltage as the gate signal for sensing while the Q node maintains a charged state on the sensing driving, wherein the first high-potential power supply voltage is higher at the time of the sensing driving than at the time of the display driving.

Abstract: A gate shift register and an organic light emitting diode display including the same are disclosed. The gate shift register includes a first stage and a second stage that output image display gate pulses during an image data writing period and selectively output a sensing gate pulse in a vertical blanking interval in which image display data is not written. The first stage includes a node Q1, a node Qbo, a node M, a first sensing control block activating the node Q1, and a second sensing control block deactivating the node Qbo. The second stage includes a node Q2, a node Qbe, a third sensing control block activating the node Q2, and a fourth sensing control block deactivating the node Qbe. The first stage and the second stage share a partial circuit necessary for driving with each other.

Abstract: A gate shift register and an organic light emitting diode display including the same are disclosed. The gate shift register includes a first stage and a second stage that output image display gate pulses during an image data writing period and selectively output a sensing gate pulse in a vertical blanking interval in which image display data is not written. The first stage includes a node Q1, a node Qbo, a node M, a first sensing control block activating the node Q1, and a second sensing control block deactivating the node Qbo. The second stage includes a node Q2, a node Qbe, a third sensing control block activating the node Q2, and a fourth sensing control block deactivating the node Qbe. The first stage and the second stage share a partial circuit necessary for driving with each other.

Abstract: An organic light emitting display, a method for driving the same, and a method for manufacturing the same are discussed. The organic light emitting display according to an embodiment includes a panel including subpixels each having a compensation circuit including a reference voltage supply transistor, which receives a reference voltage and initializes a node of a gate electrode or a drain electrode of a driving transistor using the reference voltage, a scan driver supplying a scan signal to scan lines of the panel, a data driver supplying a data signal to data lines of the panel, a timing controller that controls the scan driver and the data driver, and a reference voltage compensation unit supplying the reference voltage including a reverse voltage opposite a ripple generated in the reference voltage to the subpixels and cancel the ripple.

Abstract: An organic light emitting display comprises: a driving TFT comprising a gate connected to a node B, a drain connected to an input terminal of high-potential cell driving voltage, and a source connected to the organic light emitting diode through a node C; a first switching TFT for switching the current path between a node A and the node B in response to a light emission control signal; a second switching TFT for initializing the node C in response to an initialization signal; a third switching TFT for initializing either the node A or the node B in response to the initialization signal; a fourth switching TFT for switching the current path between a data line and the node B in response to a scan signal; a compensation capacitor connected between the node B and the node C.

Abstract: An organic light emitting display, a method for driving the same, and a method for manufacturing the same are discussed. The organic light emitting display according to an embodiment includes a panel including subpixels each having a compensation circuit including a reference voltage supply transistor, which receives a reference voltage and initializes a node of a gate electrode or a drain electrode of a driving transistor using the reference voltage, a scan driver supplying a scan signal to scan lines of the panel, a data driver supplying a scan signal to data lines of the panel, a timing controller that controls the scan driver and the data driver, and a reference voltage compensation unit supplying the reference voltage including a reverse voltage opposite a ripple generated in the reference voltage to the subpixels and cancel the ripple.

Abstract: An organic light emitting display, a method for driving the same, and a method for manufacturing the same are discussed. The organic light emitting display according to an embodiment includes a panel including subpixels each having a compensation circuit including a reference voltage supply transistor, which receives a reference voltage and initializes a node of a gate electrode of a driving transistor using the reference voltage, a scan driver supplying a scan signal to scan lines of the panel, a data driver supplying a data signal to data lines of the panel, a timing controller controlling the scan driver and the data driver, and a reference voltage compensation unit which varies the reference voltage on each scan line and supplies the reference voltage to the subpixels.

Abstract: A display device having a repair structure that makes a defective pixel operate as a normal pixel in a display panel.

Abstract: A display device having a repair structure that makes a defective pixel operate as a normal pixel in a display panel.

Abstract: A subpixel arrangement structure for a display device, including a plurality unit pixels each having a red subpixel, a green subpixel and a blue subpixel, wherein openings of the red and green subpixels of each unit pixel are aligned along a direction of a column axis, and wherein an opening of the blue subpixel of each unit pixel is aligned along a direction of a row axis that is perpendicular to the column axis or arranged in zigzags along the direction of the row axis.

Abstract: An organic light emitting display, a method for driving the same, and a method for manufacturing the same are discussed. The organic light emitting display according to an embodiment includes a panel including subpixels each having a compensation circuit including a reference voltage supply transistor, which receives a reference voltage and initializes a node of a gate electrode of a driving transistor using the reference voltage, a scan driver supplying a scan signal to scan lines of the panel, a data driver supplying a data signal to data lines of the panel, a timing controller controlling the scan driver and the data driver, and a reference voltage compensation unit which varies the reference voltage on each scan line and supplies the reference voltage to the subpixels.

Abstract: A subpixel arrangement structure for a display device, including a plurality of unit pixels each having a red subpixel, a green subpixel and a blue subpixel which form a delta arrangement structure, wherein openings of the red and green subpixels of each unit pixel are substantially aligned along a direction of a column axis, wherein an opening of the blue subpixel of each until pixel are substantially aligned along the direction of the column axis or a direction of a row axis that is perpendicular to the column axis, and wherein two of the plurality of unit pixels of each pixel group, that are positioned adjacent to each other in the direction of the column axis or the direction of the row axis, share one blue subpixel with each other.